JPH07191951A - Neural network circuit - Google Patents

Abstract

PURPOSE:To execute the processing at a high speed in a small-scale circuit and to easily extend the scale with respect to the neural network circuit for recognition processing or pictures or the like. CONSTITUTION:This multilayeted neural network circuit is provided with plural layers of networks where plural singleinput and multi-output quantized neurons are vertically branched and arranged like trees and the network in the last layer having a multi-input and single-output output neuron arranged on the top layer of these plural layers and executes the operation of networks of given feature data to perform the recognition processing. The output neuron of the network in the mast layer has the input terminal to which the output or the output neuron in the mast layer or the adjacent neural network having the same constitution is inputted as external data. Consequently, plural neural network circuits are only simply connected to present a neural network circuit whose scale can be flexibly extended, and the processing capability is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a neural network circuit for performing image recognition processing and the like.

[0002]

2. Description of the Related Art Recently, much attention has been paid to the field of neural networks for information processing. These neural networks are thought to imitate the structure of biological neurons, and most of the processing of these neural networks is realized by conventional von Neumann type sequential computers, so the processing speed is extremely slow. . Therefore, an attempt has been made to construct a dedicated electronic circuit.

There are various neural networks composed of dedicated electronic circuits, but image recognition by a network of quantized neurons (quantized cells), which is one neural network among them, is described in, for example, the literature: "Functional hierarchical network. "Character recognition system used", Annual Conference of the Institute of Image Electronics and Communication Engineers, 1990, pages 77-80, or "Mult
i-Functional Layered Network using Quantizer Neuro
ns ”ComputerWorld '90, November 1990). Image recognition by this neural network will be described below.

FIG. 12 shows a network of quantized neurons. In this network, quantized neurons are connected in a multilayer network, and the final layer has a structure in which ordinary artificial nerve cells with multiple inputs and one output are connected. The characteristic data of an image given to this network is, for example, an 8 × 8 pixel value, a horizontal difference value of 8 × 8 pixel values, and a vertical difference value of 8 × 8 pixel values. . Figure 1
As shown in FIG. 2, the first layer has 6 pixels corresponding to 8 × 8 pixels.
It consists of four quantized neurons, and pixel values are input as feature data input 1 to the quantized signal input terminals of these quantized neurons. In the second layer, the horizontal difference value of pixel values is input as the feature data input 2 to the quantized signal input terminal of the quantized neuron. In the third layer, a vertical difference value of pixel values is input as the feature data input 3 to the quantized signal input terminal of the quantized neuron. The fourth layer is a teacher input layer, and changes the synaptic coupling coefficient of each neuron in the final layer by teacher input. The final layer is the output layer of the answer, and consists of, for example, 62 ordinary artificial nerve cells for 62 alphanumeric characters.

As shown in FIG. 15, each neuron in the output layer multiplies each input data by a weight Wn (n is an input number) determined by learning, and outputs the sum of them. To do.

The quantized neuron (quantized cell) is
As shown in FIG. 13, it has a quantized signal input terminal S, a selection input terminal R, and a plurality of outputs. The signal input from the selection input terminal R is multiplied by the value x input from the quantized signal input terminal S, for example, by a weight τ according to (Equation 1), and output to each output.

Τ j = 1−β (│j-x │) (Equation 1) absolute value of │a │: a where j represents the output number of the quantized neuron.

In the quantized neuron of FIG. 13, the input level from the quantized signal input terminal S is 8 levels,
The number of outputs is 8. For example, if the function (1-β) is as shown in FIG. 16, the quantized signal input has a value 0.
Then, the values appearing at the respective outputs of the quantized neuron are the values given to the selection signal input as shown in FIG.
Is a value multiplied by the corresponding weight τ (n).

When a quantized neuron having eight quantized signal input levels S and eight outputs as shown in FIG. 13 is used to form a network, each of the eight outputs of the first layer quantized neuron is The selection signal inputs of the quantized neurons of the second layer are connected. Further, the selection signal input of the third-layer quantized neuron is connected to each of the eight outputs of each of the eight second-layer quantized neurons. In this way, when one quantized neuron in the first layer passes through the quantized neuron and branches in a tree shape, the output number (fourth layer) of the quantized neuron in the third layer becomes 512.

The quantized signal inputs of the eight second-layer quantized neurons connected to the eight outputs of the first-layer quantized neurons have the same position as the pixel value which is the first-layer feature data input 1. The lateral difference value of is given.

Each of the eight second layer quantized neurons
The quantized signal inputs of the 64 third-layer quantized neurons connected to one output are the pixel value that is the feature data input 1 of the first layer and the lateral difference that is the feature data input 2 of the second layer. A vertical difference value at the same position as the value is given.

The image recognition network of quantized neurons shown in FIG. 12 is based on one quantized neuron in the first layer and has four quantized neurons in the third layer up to the fourth layer. It consists of a tree-like network and a final layer network.

First, one layer of the quantized neuron will be described. As described with reference to FIG. 13, the quantized neuron is the output or selection signal (normally 1
Or a maximum value) and a quantized signal input S to which feature data is applied. here,
The characteristic data will be described as 8 levels from 0 to 7. At this time, the quantized neuron has eight outputs 0 to 7.

When the quantized signal input S has the value 0, the value appearing at each output is the value given to the selection signal input R multiplied by the corresponding coupling coefficient shown in FIG. 14 (a). Becomes When the quantized signal input R has the value 3, the respective coupling coefficients are as shown in FIG. FIG. 14 (b)
Is the same as sliding (3) in the same figure in the output number direction. If the quantized signal input R has the value 7,
The respective coupling coefficients are as shown in FIG. 14C, which is the same as sliding seven in the output number direction.

The maximum value is given to the selection signal input R of the quantized neuron of the first layer. For example, if the quantized neuron is operated by 8-bit operation, when the quantized signal input is 0 in the first layer, selection signal input = FF output number 0 = FF output number 1 = 7F output number 2 = 0 Output number 3 = 0 Output number 4 = 0 Output number 5 = 0 Output number 6 = 0 Output number 7 = 7F (hexadecimal notation)

The selection signal input of the quantized neuron of the second layer is given the output of the quantized neuron of the first layer. The selection signal input to the quantized neuron of the third layer is the second signal.
The output of the quantized neuron of the layer is given.

Therefore, the output of the quantized neuron of the third layer is 3 of the coupling coefficient of the quantized neuron of the first layer, the coupling coefficient of the quantized neuron of the second layer, and the coupling coefficient of the quantized neuron of the third layer. And the selection signal input of the quantized neuron of the first layer.

A configuration shown in FIG. 11 has been proposed for high-speed calculation of this neural network (application number 03-237674), and will be described below.

The conventional circuit shown in FIG. 11 is a neural network circuit which gives characteristic data to the characteristic data memories 107 to 109 and recognizes the characteristic data. That is, the network is calculated for the characteristic data.

In FIG. 11, the characteristic data memory 107
Up to 109 hold data to be given to the quantized signal inputs of the quantized neurons of the first to third layers, respectively.
The coefficient memories 101 to 103 hold the coupling coefficients of the quantized neurons in the first to third layers, respectively. The table memory 112 receives the outputs J, K, and H of the coefficient memories 101 to 103, and outputs a value obtained by multiplying them. The weight memory 118 holds the weights of the neurons in the final layer of the quantized neuron network. The cumulative multiplier 113 receives the output of the table memory 112 and the output of the weight memory 118 as input, and performs cumulative multiplication of both values.

The control circuit 117 controls the neural network circuit 1, starts processing by a start input, and operates by a clock signal. The control circuit 11
Reference numeral 7 gives the number of non-zero data Wj, Wk, Wh of the coupling coefficients of the first to third layers to the address generator 119 and the address converters 104 to 106. Address translator 104
To 106 receive respective data of the address generator 119 and the corresponding characteristic data memories 107 to 109, and perform conversion of address input of the corresponding coefficient memories 101 to 103 and conversion of address input to the weight memory 118.

The address generator 119 is composed of five counters 121 to 124, as shown in FIG. When the carry input is 1, the first layer counter 120, the second layer counter 121, and the third layer counter 122 count up from zero to the width input value −1. For example, if the width input is the value 3, it is counted as 0, 1, 2, then returns to 0, and is again counted as 1, 2. The characteristic data counter 123 is a counter that counts the number of characteristic data, and the output layer counter 124 is a counter that counts the number of outputs.

Further, in FIG. 11, the output memory 114
The value of the accumulator 113 is written in the address of the output P of the output counter 124 of the address generator 119.

Next, the operation of the conventional circuit will be described.

Characteristic data memory 107, 108, 109
The characteristic data of the image to be recognized is written in.

The output i of the characteristic data counter 123 of the address generator 119 causes the characteristic data memories 107, 1
The feature data j, k, given to each layer from 08, 109,
h is read.

The address converter 104 includes the first layer characteristic data j and the first layer counter 12 of the address generator 119.
Output x of 0, number W of non-zero data of the coupling coefficient of the first layer W
j is input. Here, for example, if the coupling coefficient of the first layer is as shown in FIG. 16, Wj is 3. The address converter 104 has an address of the coefficient memory 101 holding the coupling coefficient of the first layer quantized neuron and a part of the address of the weight memory 118 storing the coupling coefficient of the final layer neuron. Convert to.

The address conversion formula by the address converter 104 is shown below.

Output jj to address of weight memory 119
Is represented by jj = j-wj / 2 + x, and the output to the address of the coefficient memory 101 is jjj.
Is represented by jjj = -wj / 2 + x. Here, when the number of quantized neuron outputs is 8 and the level of the quantized signal input is 0 to 7, the range of the variables is 0 to 7. The lower 3 bits of the result of jjj and jj are output.

Similarly, the address converter 105 has the address of the coefficient memory 102 holding the coupling coefficient of the quantized neuron of the second layer and the address of the weight memory 119 storing the coefficient of the neuron of the final layer. It is converted into a part of and output. Similarly, the address translator 106 uses the third
It is converted into an address of the coefficient memory 103 holding the coupling coefficient of the quantized neuron of the layer and a part of the address of the weight memory 119 storing the coefficient of the neuron of the final layer, and output.

The coefficient memories 101 to 103 hold the coupling coefficients of the quantized neurons of the first to third layers, respectively, and output the coupling coefficient of the address of the input data.

The table memory 112 is the coefficient memory 10
The outputs from 1 to 103 are input, and a value obtained by multiplying them is output. That is, it becomes the output of the quantized neuron in the third layer.

The weight memory 118 holding the weights of the neurons in the final layer of the network of quantized neurons is 3
Input from each of the address converters 104, 105, 106 and the feature data counter 12 of the address generator 119.
3 and the input from the output p of the output layer counter 124 of the address generator 119, the weight of the output neuron that matches the output data of the table memory 112 (that is, the output of the quantization neuron of the third layer). Output the data.

The accumulator 113 has a table memory 11
The output of 2 and the output of the weight memory 118 are multiplied and accumulated.

The above operation is executed according to the count up of the address generator 119. Address generator 119
When the output layer counter 124 of the cumulative arithmetic unit 11 changes, the value of the cumulative arithmetic unit 113 is written to the address.
Set the value of 3 to 0.

When the count up of the address generator 119 is completed, the recognition operation is completed and the output memory 1
At 14, the solution output of the quantized neuron network is obtained.

[0037]

However, in the above-mentioned conventional neural network circuit composed of hardware, it is necessary to predetermine the number of input characteristic data to be processed and the scale of the network. It has been difficult to expand the network scale due to the complexity of.

The present invention has been made to solve the above problems, and an object thereof is to provide a neural network circuit which can be flexibly expanded in scale.

[0039]

In order to achieve the above object, in the present invention, a neural network is constructed by hardware of a certain scale and a plurality of neural networks are provided, and these can be easily connected to use the operation result. The configuration.

That is, the neural network circuit according to the first aspect of the invention is a network of a plurality of layers in which a plurality of quantized neurons each having one input and a plurality of outputs are branched vertically to form a tree, and the network is arranged further above the uppermost layer. And a final layer network having output neurons with a plurality of inputs and one output, and a final layer for a multi-layer neural network circuit that performs recognition processing by executing an operation of a network of given feature data. The output neuron of the network has a configuration having an input terminal to which external data is input.

The neural network circuit according to the second aspect of the present invention specifies the network of the plurality of layers and the network of the last layer of the first aspect of the invention, and outputs the number of networks to be calculated. Control circuit, an address generator that sequentially counts the number of networks to be calculated by the output of the control circuit, a characteristic data memory that stores characteristic data read by the address generator, and an output neuron of the final layer Of the control circuit, the feature data memory and the address generator, the weight memory for storing the weights of the And an address converter for converting into an address given to the coupling coefficient memory, and And table memory which outputs a value obtained by multiplying each input as an input the output of another of the coupling coefficient memory,
It is configured by an accumulator that cumulatively adds the output of the table memory and the output of the weight memory, and an output memory that holds the result of the accumulator at the output address of the address generator.

Further, in the neural network circuit according to the third aspect of the present invention, the elements for inputting the external data are limited, and the accumulator has a function of executing the addition of the external data by the signal of the address generator. It is designed to let you.

In addition, in the neural network circuit according to a fourth aspect of the present invention, a selection circuit for selecting either one of the table memory and the external data as an input is further provided, and the weight memory has an external selection circuit. A predetermined weight is output when data is selected, and the accumulator has a function of cumulatively adding the external data selected by the selection circuit and the predetermined weight of the weight memory and outputting the result to the outside. It is designed to let you.

[0044]

With the above construction, in the neural network circuit of the present invention according to any one of claims 1 to 4, the external data can be input to the input terminal separately provided in the output neuron of the final layer, that is, the accumulator is the external data. Since it is a configuration that executes addition of, it is only necessary to simply connect them so that multiple neural network circuits are provided and the answer output obtained by the neural network circuit can be used for addition in the final layer of other neural network circuits. It is possible to provide a neural network circuit whose scale is flexibly expanded. Therefore, if each neural network circuit has a different classification capability, the processing capability can be easily improved.

[0045]

【Example】

(Embodiment 1) A first embodiment of the present invention is shown in FIG. In the embodiment shown in the figure, the output neurons in the final layer are one input more than the output neurons in the conventional final layer as shown in FIG. 6, and the increased input weight is 1. As a result, as shown in FIG. 5, the output of the adjacent neural network is given to the output neuron of the final layer, whereby the neural network circuit is excellent in expandability.

The embodiment shown in the figure is a neural network circuit which gives characteristic data to the characteristic data memories 107 to 109 and processes the data.

The coefficient memories 101 to 103 hold the coupling coefficients of the quantized neurons of the first to third layers, respectively. The table memory 112 receives the outputs J, K, and H of the three coefficient memories 101 to 103 as inputs, and outputs a value obtained by multiplying them. The weight memory 118 holds the weights of the neurons in the final layer of the quantized neuron network.

Then, the cumulative multiplier 130 receives the output of the table memory 112 and the output of the weight memory 118 when the switching input is LOW and performs cumulative multiplication. On the other hand, when the switching input is HIGH, external addition is performed. Add the signals input from the input. The characteristic data memories 107 to 109 hold data to be given to the quantized signal inputs S of the quantized neurons of the first to third layers, respectively.

The control circuit 132 controls the neural network circuit 10, starts processing by a start input, and operates according to a clock signal.

The start output of the control circuit 132 is
The start input is delayed by one clock.

The control circuit 132 supplies the address generator 131 and the address converters 104 to 106 with the numbers Wj, Wk, and Wh of the non-zero data of the coupling coefficients of the first to third layers. The address converters 104 to 106 receive both data of the address generator 110 and the characteristic data memories 107 to 109, and the coefficient memories 101 to 1 respectively.
The conversion of the address input No. 03 and the conversion of the address input to the weight memory 118 are performed.

As shown in FIG. 2, the address generator 131
Is composed of six counters. First layer counter 120, second layer counter 121 and third layer counter 12
When the carry input is 1, 2 counts up from 0 to the width input value -1. For example, if the width input is a value of 3, it counts as 0, 1, 2, then returns to 0, and then 1,
Count as 2. The characteristic data counter 123 is a counter that counts the number of characteristic data, and the output layer counter 124 is a counter that counts the number of outputs.

Reference numeral 133 denotes an external access counter. The external access counter 133 delays the output of the characteristic data counter 123 by one clock and supplies it to the output counter 124 to calculate the calculation cycle of the external input of the accumulator 130. It is a counter that counts.

Next, the operation of the embodiment of the present invention will be described.

Characteristic data memory 107, 108, 109
The characteristic data to be processed is written in.

The output i of the characteristic data counter 123 of the address generator 131 causes the characteristic data memories 107, 1
The feature data j, k, given to each layer from 08, 109,
h is read.

The address converter 104 includes the first layer characteristic data j and the first layer counter 12 of the address generator 131.
Output x of 0, number W of non-zero data of the coupling coefficient of the first layer W
j is input. Here, for example, if the coupling coefficient of the first layer is as shown in FIG. 16, Wj is 3.

The address converter 104 is a coefficient memory 101 holding the coupling coefficient of the first layer quantized neuron.
Address and a part of the address of the weight memory 118 storing the coupling coefficient of the neuron in the final layer.

The address conversion formula of the address converter 104 is shown below.

Output jj to address of weight memory 118
Is represented by jj = j-wj / 2 + x, and the output to the address of the coefficient memory 101 is jjj.
Is represented by jjj = -wj / 2 + x. Here, when the number of quantized neuron outputs is 8 and the level of the quantized signal input is 0 to 7, the range of the variables is 0 to 7. The lower 3 bits of the result of jjj and jj are output.

Similarly, the address converter 105 addresses the coefficient memory 102 holding the coupling coefficient of the quantized neuron of the second layer and the address of the weight memory 118 storing the coefficient of the final layer neuron. It is converted into a part of and output. Similarly, the address translator 106 uses the third
The address of the coefficient memory 103 holding the coupling coefficient of the quantized neuron of the layer and the part of the address of the weight memory 118 storing the coefficient of the neuron of the final layer are converted and output.

The coefficient memories 101 to 103 hold the coupling coefficients of the corresponding quantized neurons of the first to third layers, respectively, and output the coupling coefficient of the address of the input data.

The table memory 112 receives the outputs from the three coefficient memories 101 to 103 and outputs a value obtained by multiplying them. That is, it becomes the output of the quantized neuron in the third layer.

The weight memory 118, which holds the weights of the neurons in the final layer of the quantized neuron network, receives the inputs from the address converters 104, 105 and 106 and the output i of the feature data counter 123 of the address generator 131. By the input from the output p of the output layer counter 124, the output neuron weight data that matches the output data of the table memory 112 (that is, the output of the quantization neuron of the third layer) is output.

The accumulator 130 is a table memory 112.
And the output of the weight memory 118 are multiplied and accumulated.

The above operation is executed in accordance with the count up of the address generator 131, as shown in the waveform diagram of FIG.

When the output of the external access counter 133 of the address generator 131 becomes HIGH, the carry operation C of the characteristic data counter 123 causes the accumulator 130 to operate.
Is switched to the external addition input to add external data.

After that, when the output P of the output layer counter 124 of the address generator 131 changes, the value of the accumulator 130 is written to the output memory 114 at that address, and the value of the accumulator 130 is set to 0. Then, the characteristic data counter 123, the third layer counter 122, the second layer counter 121, and the first layer counter 120 are reset.

When the count-up of the address generator 131 is completed, the recognition operation is completed and the output memory 1
At 14, the solution output of the quantized neuron network is obtained.

As shown in FIG. 3, for example, two neural network circuits 10 are provided, one circuit 10A receives 0 as external data, and the other circuit 10B accumulates the one circuit 10A. By connecting so that the cumulative calculation result of the calculator 130 is input as external data, the network as shown in FIG. 5 can be expanded. Here, as shown in the waveform diagram of FIG. 4, the circuit 10B on the side for inputting the cumulative calculation result of the cumulative calculation unit 130 as external data has a circuit 1A on the side for outputting the cumulative calculation result as external data. Operation is calculated with a clock delay.

In the network shown in FIG. 5, the input characteristic data is 128-layer data of each layer, that is, the extension is twice, but the same is true when the extension is three times or more.

(Embodiment 2) A second embodiment of the present invention is shown in FIG.
Shown in. The embodiment shown in the figure has one more output neuron in the final layer than the conventional output neuron in the final layer as shown in FIG. 10, and has a weight Ws for the increased input. As a result, as shown in FIG. 9, the output of the adjacent neural network is given to the output neuron of the final layer, so that the neural network circuit is excellent in expandability.

The embodiment shown in FIG. 7 is a circuit for processing the data given to the characteristic data memories 107 to 109.

The control circuit 132, the address generator 131,
Coefficient memories 101 to 103, table memory 112, characteristic data memories 107 to 109, address converter 104
To 106 and the output memory 114 are the same as those in the first embodiment.

The weight memory 134 is used for the address converter 10
4 to 106 outputs hh, kk, jj and address generator 1
The outputs c, i and p of 31 are used as address signals, and the weights of the neurons in the final layer of the network of quantized neurons are held.

Reference numeral 136 denotes a multiplexer. The multiplexer 136 has two inputs, that is, an external accumulative input and an output of the table memory 112, and receives the address generator 13.
When the switching input is LOW, the table memory 112 is switched by the switching signal c from 1 and the switching input is HIG.
When it is H, the external cumulative input is output. Cumulative multiplier 113
Is the output of the multiplexer 136 and the weight memory 134.
The output of is input, and cumulative multiplication is performed.

Similar to the first embodiment, it is executed according to the count up of the address generator 131 as shown in the waveform diagram of FIG. When the output of the external access counter 133 of the address generator 131 becomes HIGH, the multiplexer 136 selects the external accumulation input by the output C of the output counter 124, and outputs the value of the external accumulation input data to the accumulation multiplier 113. Output. The cumulative multiplier 113 calculates the cumulative value of the external cumulative input data and the value read from the weight memory 134. At this time, the value read from the weight memory 134 is the value of the weight Ws in FIG. After that, when the output P of the output layer counter 124 of the address generator 131 changes, the accumulator 11 is assigned to the address.
The value of 3 is written to the output memory 114, and the accumulator 11
Set the value of 3 to 0. Then, after that, the characteristic data counter 123, the third layer counter 122, and the second layer counter 12
1, the first layer counter 120 is reset.

When the count-up of the address generator 131 is completed, the recognition operation is completed and the output memory 1
At 14, the solution output of the quantized neuron network is obtained.

This neural network circuit 11 is shown in FIG.
By connecting in the same manner as above, the network shown in FIG. 9 can be expanded. In the network shown in FIG. 9, the input feature data is 64 data for each layer, but the left and right neural networks are provided with different classification capabilities, and the respective results are weighted and added to obtain the final answer output. The ability of the neural network can be improved.

In the above description, the network using the quantized neuron is used for the feature data of one layer of 8 × 8 6
Although it has been described as the feature data of 4 layers and 3 layers, and the output of 64 answers, the present invention is not limited to this.

[0081]

As described above, according to the present invention,
In the neural network circuit using the quantized neuron, the neural network was constructed with hardware of a certain scale and configured so that it could be externally input, so it is only necessary to provide multiple neural networks and simply connect them. It is possible to provide a neural network circuit whose scale can be flexibly expanded, and to realize a neural network circuit with improved processing capability.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a neural network circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an address generator according to the first embodiment of the present invention.

FIG. 3 is a connection diagram when a plurality of neural network circuits according to the first embodiment of the present invention are used.

FIG. 4 is a waveform diagram of each part in the connection of FIG.

FIG. 5 is an explanatory diagram of a neural network model in the connection of the neural network circuit FIG. 3 according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of neurons in the final layer of the model of the neural network circuit according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a neural network circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of an address generator in a neural network circuit in a conventional example.

9 is an explanatory diagram of a neural network model in the connection of FIG. 3 of the neural network circuit according to the second embodiment of the present invention.

FIG. 10 is an explanatory diagram of neurons in the final layer of the model of the neural network circuit according to the second embodiment of the present invention.

FIG. 11 is a configuration diagram of a neural network circuit in a conventional example.

FIG. 12 is an explanatory diagram of a structure of a neural network including quantized neurons in a conventional example.

FIG. 13 is an explanatory diagram of a quantized neuron.

FIG. 14 is an explanatory diagram of quantized neuron coupling coefficients.

FIG. 15 is an explanatory diagram of neurons in the final layer of the neural network using quantized neurons.

FIG. 16 is an explanatory diagram of quantized neuron coupling coefficients.

[Explanation of symbols]

 101-103 Coefficient memory 104-106 Address converter 107-109 Characteristic data memory 112 Table memory 113,130 Cumulative calculator 118,134 Weight memory 117,132 Control circuit 119,131 Address generator 120 First layer counter 121 Second Layer counter 122 Third layer counter 123 Characteristic data counter 124 Output layer counter 133 External access counter 136 Multiplexer

Claims (6)

[Claims] 1. A final network having a multi-layer network in which a plurality of one-input multi-output quantized neurons are vertically branched and arranged in a tree shape, and a multi-input one-output output neuron arranged further above the uppermost layer. And a network of layers, which is a multilayer neural network circuit for performing recognition processing by executing an operation of a network of given feature data, wherein external neurons are input to output neurons of the network of the final layer. A neural network circuit having an input terminal according to claim 1. 2. The multi-layer network and the final layer network each include a control circuit that outputs the number of networks to be calculated, and an address generator that sequentially counts the number of networks to be calculated by the output of the control circuit.
A feature data memory that stores the feature data read by the address generator, a weight memory that stores the weight of the output neuron of the final layer, and a layer other than the final layer that stores the coupling coefficient of neurons other than the final layer. Coupling coefficient memory, an address converter for converting the outputs of the control circuit, the feature data memory and the address generator into an address given to the weight memory and an address given to the coupling coefficient memory, and the coupling coefficient for each layer. A table memory that outputs a value obtained by multiplying each input by using the output of the memory as an input, an accumulator that cumulatively adds the output of the table memory and the output of the weight memory, and the accumulator at the output address of the address generator. The neural network according to claim 1, further comprising an output memory for holding a result of the arithmetic unit. Circuit. 3. The neural network circuit according to claim 2, wherein the accumulator has a function of executing addition of external data according to a signal from the address generator. 4. A selection circuit having a table memory and an external data as an input and selecting one of them,
The weight memory outputs a predetermined weight when the selection circuit selects external data, and the cumulative calculator cumulatively adds the external data selected by the selection circuit and the predetermined weight of the weight memory. 3. The neural network circuit according to claim 2, wherein the neural network circuit outputs it to the outside. 5. A neural network circuit according to claim 3 or a plurality of neural network circuits according to claim 4, wherein two adjacent neural network circuits are cumulative results of a cumulative computing unit of one of the neural network circuits. Is output as external data to the other neural network circuit. 6. The operation of the neural network circuit on the side where the cumulative result of the cumulative operator is input as external data is delayed by one clock from the operation of the neural network circuit on the side where the cumulative result of the cumulative operator is output. 6. The neural network circuit according to claim 5, wherein