SU758517A1 - Multichannel electronic searching counter - Google Patents

Description

one

The invention relates to computing and can be used to build parallel-sequential switching and 5 summing devices in universal and specialized output systems and high performance structures.

The closest technical solution to this invention is a multichannel electronic finder-counter that contains a key, an OR element, a NOT element, switching blocks, each of which consists of j AND element, two triggers, three keys and delay element I,

The disadvantage of this multichannel counter-seeker is the low speed in generating the values of jQ for the sum of the increments.

The aim of the invention is to improve the speed in the formation of the sum of the increments.

The goal is achieved by the fact that 25 a multichannel electronic counter-finder contains a key, the control input of which is connected to the output of the NOT element, the input of which is connected to the first input bus JQ

key output is connected to the device’s information output bus, and the key signal input is connected to the output of the OR element, whose inputs are connected to the information output buses of two switching blocks, each of which consists of the first element AND, the first input of which is connected to the information input bus and the signal input of the first key, the second input of the first element I is connected to the first input bus control, the third input is connected to the information output bus of the device, and the output of the first element I is connected to the unit the input of the first trigger, the zero input of which is connected to the second input control bus, the direct output of the first trigger connected to the control input of the first key, the output of which is connected to the single input of the second trigger, the zero input of which is connected to the output of the delay element, the direct output of the second trigger connected to the control input of the second key, the output of which is connected to the information output bus of the switching unit, the inverse code of the second trigger is connected to the control input of the third key, signal second and third inputs of the keys of the first switching unit connected to the third control input bus, a second - a yield of a third key of the first switching unit; Fourth, fifth and sixth control buses, each of the switching blocks additionally four AND elements and two OR elements, and the inputs of the first OR element are connected to the output of the second key and the outputs of the second and third AND elements, the output of the first OR element of the first switching unit is connected to the first inputs of the second and fourth elements 4 of the second switching unit, the output of the first element OR of the second switching unit is connected to the first output control bus, the second input of the second element AND is connected to the investment to the second output of the second element I, the third input of the second element I to the first input of the third element I and to the fourth input control bus, the output of the first element OR connected to the input of the delay element, second input of the third element And is connected to the forward second trigger and to the second input of the fourth element AND, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the fifth AND element, the output of the second OR element of the first switching block chen to the second input of the fifth AND gate and to the third input of the third element and the second switching unit, the output of the second OR gate of the second switching unit is connected to the second output of the control bus, the first and second inputs. the fourth elements AND of the first switching unit are connected to the fifth control input bus, the second input of the fifth element AND and the third input of the third element AND of the first switching unit are connected to the sixth input control bus, the output of the third key of the second switching unit is connected to the third output control bus.

The drawing shows a circuit diagram of an electronic searcher of a multichannel counter, made in accordance with the present invention.

The multichannel electronic finder-counter contains the element NE-1, the element OR 2, the key 3, the switching blocks 4,5, each of which consists of the elements AND 6-10, - the elements OR 11-12, the keys 13-15, the delay element 16 , triggers 17, 18, input information bus 19 output information bus 20; control tires - assembly bus 21, reset bus

22, summation resolution bus 23, increment sum unit value bus 24, output step unit formation unit value 25, increment formation bus line 5 zero sum increment value 26, output output tire value zero sum value increment 27, read value read bus 28, output output bus increments 29 and Q output information bus device 30.

The multichannel electronic finder-counter can be expanded by sequentially connecting n-switching blocks,

5 Works multichannel electronic finder-counter as follows.

In the first cycle, the triggers 17 and 18 of each switching unit 4, 5 are reset to the zero state. For this, single signals are sent to the reset bus 22 and the increment read bus 28. The first of them goes directly to the zero inputs of the flip-flops 17 and sets them to the 5th zero state, while the second goes to the combined signal inputs of the keys 14 and 15 of the switching unit 4. If one is recorded in the trigger 18 of the switching unit 4, the Q 14 key is opened The signal arrives at the KOTOEM signal to the element OR 11. From the output of this element, the signal passes through the delay element 16 to the zero input of the trigger 18. From this moment on, the prog will reset the trigger 18 of the switching unit 4 to the zero state. After resetting the flip-flop 18 to the zero state, key 15 is unlocked, and key 14 will be closed and C out; yes, key 15, the signal goes to 0 the combined signal inputs of keys 14 and 15 of the next switching unit 5. The process repeats until the flip-flops 17 and 18 of all switching blocks are not set to zero 5 state and on the output bus of the readout of increments 29 a pulse is not heard.

In the second cycle, the units are recorded in the triggers of 17 branded switching blocks.

Sampling is done by supplying single signals to the input information buses 19 of the corresponding switching blocks 4, 5 and bus f of the assembly 21. As a result,

element & b of the selected commutation. the main unit, the signal sets the trigger 17 in a single state.

Claims (1)

1. USSR author's certificate No. 499665, cl. H 03 K 17/04, 1974 (prototype). About About About 2/22 23 2428гВ