SU744935A1 - Device for discriminating single pulse - Google Patents

Description

one

A device for isolating a single pulse relates to a pulse technique and can be used in various devices for converting, processing and transmitting information.

A clock synchronization device is known that contains two series-connected V-triggers, an NAND element, the first input of which is connected to the clock input of the first trigger, the second input of the NAND element is connected to the single output of the first trigger, the zero output of the first trigger is connected to the second input a trigger whose clock input is connected to the output of the NAND element, and a single output of the second trigger is connected to the third input of the NAND element 1. A device that has a higher noise immunity has creatures nny disadvantage that the time they develop the clock pulse can reach values of 1.5 T, where T - 20 clock cycle. This leads to a significant decrease in the speed of the device, moreover, at its output a pulse of only negative polarity is emitted, which limits the applicability of the circuit.

Of the known devices, the closest in technical essence is a device for extracting a single pulse 2.

This device contains a S-flip-flop, a D-flip-flop, the information input of which is connected to a control signal source with a single input1 of a 5-flip-flop, a single output of which is connected to a zero input of a D-flip-flop, and a zero input - with an output of an NAND gate, whose first input connected to the output of the inverter, and the second to the single output of the B-flip-flop, which is the output of the device. The circuit of this device is simple and allows you to receive a direct and inverse pulse at the output, but if the input control signal coincides with a pulse action time clock, the device generates a single pulse at the output of only the second clock pulse, which leads to time consuming, reaching a value of 1.5 T, and thereby reduces the performance of the device.

The aim of the invention is to increase speed.

The goal is achieved in that a device containing an RS-TpHrrep, B-flip-flop, whose information input is connected to a control signal source and a single N-flip-flop input, a single output of which is connected to the zero input of the D-flip-flop, and a zero input to the RS-flip-flop connected to the output of the NAND element, the first input of which is connected to the output of the inverter and the second input - to the single output of the B-trigger, the clock input of which is connected to the input of the inverter, additional D-flip-flop, RS-flip-flop, inverter, three two-input elements And -NOT The delay element, the clock input of the first D-flip-flop and the input of the first inverter are connected to the output of the second NAND element, the first input of which is connected to the output of the third NAND element connected by the first input to the clock source, the input of the second inverter, clock and information inputs of the second D-flip-flop, the unit output of which is connected to the second input of the third NAND element, and the zero input of the second D-flip-flop is connected to the output of the fourth NAND element and through the delay element to the second input of the second AND element NOT, the first input of the fourth NAND element is connected to the output of the second inverter and the single input of the second S-trigger, the zero input of which is connected to the control signal source, and the output to the second input of the fourth AND NAND element.

FIG. 1 is a schematic of a device for isolating a single pulse; in fig. 2 shows the diagrams characterizing the operation of the device.

The device contains NAN-triggers 1 and 2, D-triggers 3 and 4, logic gates AND-NOT 5, 6, 7, 8, inverters 9 and 10, delay element 11, 12 clock input, control input 13, my output 14 and inverse output 15.

The principle of operation of the device is as follows.

The device emits a single pulse synchronously with a clock frequency impulse or with a clock pause, depending on the moment of arrival of signals at inputs 12 and 13. If the arrival time of the input control signal at input 13 does not coincide with the time of the operation of the pulse at input 12, then on the leading edge of the first clock pulse, trigger 3 is set to one state and gates the clock pulse to pass through the AND-NOT 6 elements to the input of the AND-NE element 7 that performs the logical function OR at low ur ram of the signals, and then to the clock input of the B-trigger 4 and the inverter 10.

In this case, prior to the arrival of the input control signal, the trigger 1 is set low at its zero input to the zero state, which ensured the presence of a single logical signal at the output

element AND-NOT 5, contributing to the passage of a clock pulse. The leading edge of this pulse records in trigger 4 single information supplied to its information input by an input control signal, which corresponds to the appearance

® at the output of the device of a single pulse, the leading edge of which is formed on the falling edge of the clock pulse, which establishes through the inverter 10 and the AND-HE element 8 trigger 2 to the zero state,

low potential from the output of which resets trigger 4. Each subsequent clock pulse cannot change the state of the device until a new control signal arrives, since trigger 2 remains in the zero state until the end of the main control signal.

In the case of an input control signal during the operation of a clock pulse, the unit information will not be recorded by this pulse into trigger 4, since this is possible only by the leading edge of the pulse. At the same time, the trigger 1 is set up by a clock pulse inverted through the inverter 9 into a single state and remains in this state.

 state in the presence of the input control signal. After the termination of the clock and the pulse frequency at the output of the inverter 9, a positive level is formed, creating a low potential at you during the AND-HE element 5, which sets the trigger 3 to the zero state and maintains it in this state until the input control signal expires which prohibits the passage of clock pulses

Claims (2)

0 through the element AND-NOT b on the element AND-NOT 7. At this moment, the coincidence on the element AND-NOT 7 of a high voltage level coming from the element AND-NOT b and delayed by the delay element 11 and the pulse frequency creates a negative differential voltage at the output of the element AND-NOT 7 for a time equal to the delay of the element I. After that, the ps delayed leading edge of the clock frequency pause is formed at the output of the element AND-NE 7 the leading edge of the clock pulse, the leading edge of which is formed on the leading edge of the next clock pulse frequencies. The generated clock pulse is allocated at the output of the device in the same way as described above. Thus, the maximum time required to form the output pulse is no more than one clock period T. The device for extracting a single pulse favorably differs from the known ones, so that regardless of the arrival timing of the input control signal of the clock pulses, the device stably forms the output pulse impulse along the nearest clock voltage differences. At the same time, while maintaining high noise immunity of the device, it was reduced by the need for receiving the output signal after the input control signal was applied, which increases the device speed by 1.5 times. The listed advantages of the device expand its sphere of application. Apparatus of the Invention A device for extracting a single pulse, containing 1 8-flip-flop, B-flip-flop, whose information input is connected to a control signal source and a single IQ-flip-flop input, whose single output is connected to zero input of D-flip-flop, and zero input to RS-flip-flop connected to the output of the element IS-NOT, the first input of which is connected to the output of the inverter, and the second input - to the single output} of the trigger, the clock input of which is connected to the input of the inverter, characterized in that, in order to increase speed, JTV-, I HI I ILI iUJIraL153.TUDTS.11 - ..: 1D MIAIG. Introduced, complete the P1 trigger, | 3-trigger inverter, three two-way AND-NOT elements, and a delay element, for this, the clock input of the O-flip-flop is connected to the output of the first additional AND-NOT element, the first input of which is connected to the output of the second additional AND-NE element, the first input of which connected to a clock source, an additional inverter input, clock and information inputs of an additional D-trigger, the single output of which is connected to the second input of the second. additional element AND-NOT, and the zero input of an additional trigger is connected: 1nen with the output of the third additional element ME and through the delay element with the second of the first additional element NAND, the first input of the third additional element NAND is connected to the output of the additional inverter and the single input of the additional RS trigger, the zero input of which is connected to the control source signal, and the output with the second input of the third additional element AND-NOT. Sources of information received in Bivmaki at the examination 1. Authors certificate of the USSR 544115, cl. And 03 K 5/13, 07.14.75. 2. USSR author's certificate number 595852, cl. And 03 K 3/78, 07/19/76. p --- y r I 1JtJ J b -., -. i.-..-..-- .. “en Ta moBaff frequency Control signal Bb / jfodHoJ signal T Clock frequency / correct signal Output signal