RU1830531C - Device for subtraction of sequences of two pulse trains - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in automatic control and information processing systems. The purpose of the invention is to simplify the device and expand the functionality. The device contains a sign trigger, two NAND elements, a clock generator containing Schmitt trigger connected in series, two narrow pulse shapers, each of which contains two D-triggers, and two subtractors. 2 ill.

Description

(/

WITH

The invention relates to the field of automation and computer technology and can be used in automatic control and information processing systems.

The purpose of the invention is to simplify the device and expand the functionality.

In FIG. 1 shows a diagram of the proposed device, and in FIG. 2 is a time diagram of its operation.

The device consists of a clock generator 1, two formers 2, 3 narrow pulses, two subtractors 4, 5, and the clock generator 1 contains a series-connected Schmitt trigger 6 and a countable D-trigger 7. whose direct and inverse outputs are the first and second, and the Schmitt trigger output with 6-third outputs of the clock generator 1, each of two shapers 2, 3

narrow pulses contains two D-flip-flops 8. 9 and 10, 11, the direct output of the first D-flip-flop 8 (10) is connected to the C-input of the second D-flip-flop 9 (11), the S- and D-inputs of which are connected to the unit potential bus, the direct and inverse outputs of the second D-flip-flop 9 (11) are the first and second outputs of the narrow pulse shapers 2 (3), the D-inputs of the first D-flip-flops 8, 10 are connected respectively to the first and second input buses of the device , and the R-inputs of the second D-flip-flops 9. 11 are connected to the third output of the clock frequency generator 1, and each of the two subtractors 4 and 5 contains D-t rigger 12 (13), the D-inputs of which are connected to the bus of zero potential, and the inverse outputs are connected to the first inputs of AND-NOT 14 elements (15), the outputs of which are connected to the outputs of the subtractor 4 (5), the first outputs of the first and second

00

so o eat

Cj

shapers 2, 3 narrow pulses are connected respectively to the first inputs of AND-NOT elements 14 and 15 of the first and second subtractors 4 and 5, the second output of the first shaper 2 narrow pulses is connected to the C-input of the D-trigger 12 of the first subtractor 4 and S-input O -trigger 13 of the second subtractor 5 and with the first input of the AND-NOT element 16, the S-input of the D-trigger 12 of the first subtractor 4 and the C-input of the D-trigger 13 of the second subtractor 5 are connected to the second output of the second driver 3 narrow pulses and with the second input element AND 16, the outputs of the subtractors 4 and 5 are connected respectively It is connected with the S- and R-inputs of the trigger of sign 17 and with the inputs of the first element AND-NOT 18.

The device operates as follows.

The Schmitt trigger 6 at the output 19 generates a pulse train with a frequency exceeding by two orders of magnitude the maximum frequency of the input pulse sequences fi and f2. At the direct 20 and inverse 21 outputs of the D-flip-flop 7, pulses are shifted relative to each other by half the period with a frequency that is halved than at the output 19 of the Schmitt trigger 6.

With the advent of pulse sequences at the inputs of the L-flip-flops 8 and 10, the outputs 22 and 24 are switched, and thereby the outputs 23 and 25 of the O-flip-flops 9 and 11 are set to one. In this case, the switching moments of the O-flip-flops 8-1T are synchronized by pulses from the outputs 20 and 21 of the D-flip-flop 7. The same state at the outputs 23 and 25 of the D-flip-flops 9 and 11 is maintained during the time of supplying a single signal from the output 19 of the generator 1 clock frequencies to the R-inputs of the D-flip-flops 9 and 11. A zero signal from the output 19 of the clock generator 1 switches the outputs 23 and 2.5 of the D-flip-flops 9 and 11 to the zero state, and narrow pulses with a pulse duration are formed at the outputs 23 and 25 generator 1 clock frequencies that do not match and are shifted from each other during at least for the period of the switching frequency of the Schmitt trigger 6, Single pulses are generated at the outputs 26 and 28 with durations equal to the time intervals from the moment of arrival of the pulses at the C inputs to the disappearance of the pulses at the S inputs of the D triggers 12 and 13. Repeated pulses arriving at the indicated intervals at one of the inputs S or C do not change the state of the D-flip-flops 12 and 13, however, they pass through one of the NAND 14 or 15 elements to the outputs 27 or 29, and then through the element

NAND 18 to output 30, where a frequency difference of two pulse sequences () is generated. In this case, the sign of the frequency difference is determined by the output signal of the sign 17 trigger, and at the output 31 of the AND-NOT 16 element, the sum of the frequencies of the pulse sequences (fi + fa) is formed.

Claims (1)

The claims A device for subtracting the frequencies of two pulse sequences containing a sign trigger, two NAND elements and a clock generator, characterized in that, in order to simplify and expand the functionality, it contains two narrow pulse generators, each of which contains two D-triggers , the direct output of the first of which is connected to the C-input of the second, S- and D-inputs which are connected to the unit potential bus, the direct and inverse outputs of the second D-flip-flop are the first and second outputs of the narrow pulse former, and the D-inputs of the first D-flip-flops connected respectively to the first and second input buses of the device, the first and second outputs of a clock generator containing Schmitt trigger and counting trigger connected in series, connected respectively to the C-inputs of the first D-flip-flops of the first and second narrow pulse shapers, and the third output of the clock generator connected to the output of the Schmitt trigger, connected to the R-inputs of the second D-flip-flops of narrow pulse shapers, two subtractors, each of which contains a D-flip-flop, the D-input of which is connected to the zero potential bus, and the inverse output is with the first input of the AND-NOT element, the output which is connected to the output of the subtractor, and the first outputs of the first and second narrow pulse shapers are connected respectively to the first inputs of the NAND elements of the first and second subtracters, the second output of the first narrow pulse shaper is connected to the C-input of the D-trigger of the first subtractor and S-input by the D-trigger of the second subtractor, the S-input of the D-trigger of the first subtractor and the C-input of the D-trigger of the second subtractor are connected to the second output of the second narrow pulse driver, the outputs of the subtractors are connected respectively to S- and By the R-inputs of the sign trigger and with the inputs of the first AND-NOT element, the inputs of the second AND-NOT element are connected to the second outputs of the first and second narrow pulse shapers. / gp & iCQoesi