SU744548A1 - Code converter - Google Patents

Description

(54) CODE TRANSMITTER 1, The binary to binary or binary to binary to binary number converter in the whole field of the representation of real numbers is related to digital computing and can be used in computers and specialized automatic devices. A device for transcoding discrete information is known. holding a memory cell of n - bit binary code, block P1 "about} of generation of values of binary code bits, individual weight equivalents of the decimal number system, one decade decimal sum, node of the operating memory, block of reading and conversion of the adder code in the given code, reference signal generator, time distributor of synchronization signals and node formation of instruction commands 1. The device implements only the function of converting positive binary codes into binary-decimal ones. In addition, this device has low speed due to the sequential conversion of the weight equivalents of the decimal system .; The counting of each binary bit into a number-pulse code, equal to the weight equivalent of this bit, and the summation of this code on a sequential decimal adder, the conversion of this device depends on the bit size and byd. code to be converted. The average conversion time for a 30-bit binary code and a clock frequency of 5 MHz is 1 MKS. The known converter is a binary code of a binary code to a serial binary code, a sbrebryshchy serial, a switch, an input register, pa; a distributor of pulses, a sign trigger and logic elements AND and OR. The known producer implements the function of converting positive and negative binary-decimal codes into binary ones 21. However, the use of a sequential adder leads to an increase in the conversion time. The closest technical solution to the proposed, i used general principle of conversion is a converter of a binary-decimal code into a serial binary code containing a register of a soft code, a trigger; sign, pulse distributor, adder, adder regis ;, additional register, logical elements AND or OR and foror of equivalent equivalents, the information inputs of which are connected to the outputs of the register of the input code, and the outputs with the first group of inputs of the adder. The outputs of the adder are connected to the inputs of the register of the adder, whose outputs are connected to the inputs of the additional register, and its outputs are connected to the second group of inputs of the adder. The control of the input groups of the driver is connected to the outputs of the pulse distributor. 3 The disadvantage of the converter is that it leaves only the conversion of binary-decimal positive and negative codes into binary ones. The purpose of the invention is to expand the functionality of the converter by converting positive and negative binary to binary and binary to binary-decimal codes. This goal is achieved in that the code converter contains an input code register with a character; the discharge, pulse distributor, adder, register and shaper of equivalent equivalents, whose information inputs are connected to the outputs, the input code register, and the outputs are connected to the first group of inputs of the adder, the second group of inputs is connected to the outputs of the register, the control inputs of the ramifier and regis ; gra connected to the outputs of the pulse distributor, the first register of the shift of the adder, the second register of the shift of the adder, an additional register, a block overflow correction and encoder correction code, input Which are connected to the outputs of the register, and the outputs are connected to the first group of inputs of the adder, the inputs of the second register of the shift of the adder and four inputs of the lower bits of the first register of the shift of the adder are connected to the corresponding outputs of the adder, the output of the higher-order discharge of the adder is connected to the input of the higher resolution Yes, the first shift register of the adder, the serial input of the second shift register of the adder is connected to the output of the low-order bit of the first shift register of the adder, the outputs of the first shift register, the adder S connected to the inputs of the register, outputs: the second register of the shift of the adder Connected to the inputs of the additional register, the outputs of which are connected to the second group of inputs of the adder, the outputs of the three most significant bits of the additional register are connected to the first, second and third input of the overflow correction block, the fourth input of which connected to the output of the senior, the bit of the first shift register of the adder, and the outputs of the overflow correction block are connected to the first group of the input of the adder, the additional output of the correction block by erepolneniyu connected to a further input of the adder, the control inputs of the encoder correction code correction unit overflow, shift registers and auxiliary register adder connected to the outputs ate distribute momenta. The drawing shows a block diagram of the Converter. The code converter contains adder 1, shaper 2 of one equivalent equivalents, input code register 3, pulse distributor 4, first adder shift register 5, second adder shift register b, additional register V, overflow correction block 8, correction code encoder 9 and the register Y. In table. 1 shows the binary-decimal equivalents of binary numbers.

Table

744548

Tab. 4 illustrates the process of converting binary code.

eight

0.01101100111111 6 is a binary-decimal number.

Table 4

- / Continuation of table 4

1,2 f

0001 00011 2

3

four

5.6 pool 00010 b.

7 8

9.10 1. 0001 oooio

10 11.

12 13.140000 00001

14

15

16 17.18.00000

18

2001001

21

2201001

23

24

00000000.0

1.2

2

3

4 5.6 000. 1 00001

6

7

eight

000100001

9,10 10

11 12 000000000

13.14 1.4 15

sixteen

o, o o, 0 17.18 18 20 21 22 23 24

00110 00110

Converter codes works as follows.

Inputs A of the discharge adder 1 are connected via-, the A-bus of the term to the outputs of the former 2 bitwise equivalents. The number of outputs of the imaging device is 2, and, therefore, the size of the adder depends only on the size of the code being converted, but not on its form. The inputs of the imaging unit 2 are connected on one side with the outputs of the register 3 of the input code, and

00011

00001 1000.

about about 1

00010 00001 0100

0001

00010 00001 0010

0001

00001 00000 1001

0000 1001

00000 00000 1001

0000 1001

00000 10-01

I 1 001

00000 00000 0000

0000

00001 00000 1000

0000

00001 00000 1100

0000

00000 00000 0110

0000 0110

00000 00000 0110

0000 0110

00000 0110

| 0 1 1 01

- with the outputs of the distributor s, the number of outputs of the KotN RC + 24 T ;,

Claims (2)

the number of cycles equal to the number of bits of the converted code; the number of ticks in each cycle when converting a binary code to a binary one. The output of each bit of the summator is U 1Sh gTT11ёrenoea H:; about sgarshyogb1Gazr Soyineni with the input of the corresponding bit of the shift register 5.summator, four ml; the first register 5 of the sum of the mat is connected to the serial input of the second register 6 of the shift. The outputs of register b are connected to the corresponding inputs of the additional register 7, the outputs of the three higher races of which are connected to the inputs of the overflow correction unit 8. The outputs bd, co, do scheme 8, via the bus A of the term are connected to the inputs A, AJ and AJ of the adder. Shlokho RO overflow correction block is connected to the input RO of the suction side 1. All outputs of the first shift register, with the exception of the high bit, are connected to the inputs of the register 10, the high bit of it is connected to the fourth input of the block 8. The outputs of the 10 are connected to the inputs of the encoder Correction Code 9, and JD entry; , ci, d, a, .b, with the plugs of the term A connected to the corresponding inputs of the adder I. At the same time, the outputs a b, CQ, Af, register 7 And the outputs a, C, c, d register 10, through the bus Addendum B is connected to the inputs V, U, B, B of the adder. The control inputs of registers 5, b, 7, 10, circuits 8, and also the encoder 9 are connected to the outputs of the distributor 4. ..., „. . - „.,. The operation of the proposed transformation body is described for the case of converting a binary code into a binary-ten code. ... By the command Conversion type Input of the distributor 4 receives the input frequency (), by means of which the valve 4 produces a number of cycles equal to the width of the converted binary-decimal code and in each cycle there are 24 such pulses and also sets S zero state registers 5, 6, 7, and 10 — During the 1st and 2nd clock pulses of the first cycle of the pulse distributor, the binary position of register 3 with the weight of 2 driver 2 is interrogated. At the same time, the outputs of the imaging unit are connected / through the Tyins of the addendum, And to the inputs A of the adder 1, to the inputs B, through the buses of the addendum B, the outputs of the register 10 are connected and an additional output PO of the unit 8 is connected to the additional input PO. Thus, the output of the imager forms binary 4-bit code (term A) for the case of converting a 30-bit binary code equal to the value of bit 2 The former performs the function of converting single-weight units of the requested bits into a binary 4-bit code. If the polled bit with a weight of 2 ° is one, then the output of the imaging unit will be a binary code equal to 0001. The term B is equal to 0000, since register 10 is set to the zero state. At the additional input, the PQ adder 1 will also be O, since the most significant bit of register 5, connected to the input RO of the adder is 1-2t ras. The pulse converter through overflow correction block 8 is equal to O. Block 8 operation is explained by the truth table (Table 2). Consequently, the output of adder 1 will be code 00001. W6) eye clock pulse (2T), four lower bits of the adder are written to the first shift register 5, the third clock pulse (ST) simultaneously shifts the contents of the first and second shift registers 5 and b one bit to the right. Thus, the first shift register 5 will be in the zero state, and the low-order unit will go to the high bit of the second shift register b. Fourth cycle (4Т) zero state of 4 lower bits of register 5 is rewritten into register K). During time 5 and b-th cycles, register bits 3 are polled with weights of 2, 2, 25, 28, i, 2, 2, 2, 1 52-, 2Y, 29. f. t t, f t I t T.-e. in accordance with table.1. At the same time, the outputs of the imaging unit are connected via the buses of the term A to the first group of inputs of the adder, to the second group of inputs the outputs of the register 10 are fed, as well as a survey of the register 3 with a weight 2. If If we assume that all these bits are equal to one, then the output of the driver will be code 1111, i.e. 15 units expressed by binary code. By the sixth clock pulse, the contents of the adder are rewritten to the first shift register 5. The seventh is the shift of the contents of registers 5 and 6, i.e. register 5 is equal to .11100, and register b is UN. The eighth clock cycle, the contents of the 4 lower bits of register 5 are rewritten into register 10. Consequently, the contents of register 10 are 1110. During the 9th and 10th clock pulses, pulses are polled in column c., - 2 first digits of Table 1, The addition of the contents of the register 10 and the output of the former is made. The result is written to register 5, the eleventh cycle is to shift the registers 5 and 6, the twelfth is to write. Column d | 2 of the first digit is polled to register 1013-14t and the contents of register 10 are added to the driver outputs. The fourteenth cycle records the result of the addition to the register 5. The fiveth cycle is the shift of the registers 5 and b. By the sixteenth, the contents of registers 5 and 6 are recorded on registers 10 and 7. Thus, by the sixteenth clock and pulse on registers 7 and 10, we have information on the number of units in the number to be converted, expressed by a binary code, the value of which for a 30-bit binary the code does not exceed 143. Now it remains to select the number of ones from the total number of units, expressed in binary-decimal code. This operation is performed as follows. The correction code encoder 9 generates the three most significant bits of the correction code a, b, c, and the three least significant bits bj, co, do. The operation of the encoder 9 is shown in the intensity table (Table 3). The inputs of the encoder are permanently connected to the outputs of the register 10. During the 17th and 18th cycles, the outputs of the higher bits of the corrective code are sent to the inputs AJ ,, A and AJ of the adder, respectively, through inputs 6 of the register 10 There is an addition of the 4 high bits of the binary code of the number of units with the high bits of the correction code. At the same time, the overflow signal from the PQ output of block 8 is fed to the input P of the adder, if register 7 is greater than or equal to 10, the result of addition that does not exceed 140 units, i.e. the output P of the sum of the matrix is equal to O, recorded by the eighteenth clock cycle on register 5, after which the outputs of register 10 are disconnected from the buses of term B. At the time of the 19th to 23rd cycles, the outputs of register 7 are connected via the buses of the addendum & to the inputs of the adder. At the time of the 19th – 20th cycles, the corresponding digits of the correction code of the encoder 9 are applied to the inputs A, A, and A of cyMMaToi, respectively. Register 7 is added to the lower bits of the correction code. The information of the four low-order bits of the adder is written to register b by the twentieth clock, and the output Pj of the adder records to the upper split of register 5. Twenty-first cycles from the contents of registers 5 and b are rewritten to registers 10 and 7. This information in register 10 is used in the following cycle, and the information in register 7 is subject to final adjustment, i.e. the contents of register 7 are added to the output of circuit 8. For this, for the time of the 22nd – 23rd clock, the outputs b, c, d of block 8 are fed through the buses of term A and respectively to the inputs A, Aj and AJ of the adder. The sum is recorded with 23 clock per register 6. The output of the adder's Pg is recorded in the most significant bit of register 5 with the same clock if at that time it is in the unit state. By the twenty-fourth cycle, the contents of register b are rewritten to register 7. This information is the binary-decimal code of the tetrad of units. Subsequent bits are generated in the same way, only the polled bits of the register correspond to Table 1. The conversion of the additional binary code is performed in the same way as the direct one, except that the inverse code of the number being converted is fed to the input of the imaging unit 3 and the sign is interrogated during 1-2T of the first cycle. In order to clarify the operation of the converter in the conversion of a binary code to a binary-decimal, let us consider an example of converting a binary code 0.01101100111111 (Table 4). The positive effect of the invention is to expand the functionality, i.e. in the possibility of converting both binary codes to binary-decimal and binary-decimal to binary in the entire field of real numbers on one device. The equipment and power consumption of the vehicle shortage is approximately doubled, which leads to an increase in the reliability of the device. The time for converting a binary code to binary is shortened f by 20 times. The proposed code converter performs the operation of converting a D-bit binary code to a binary-decimal in 50 µs, and a 9-bit binary-decimal code to binary in 25 µs at a frequency of the master oscillator 5 MHz. Claims converter containing the input code register with a sign bit, pulse distributor, sumttor, register and form, a size equivalent, the information inputs of which are connected to the outputs of the register of the input code, and the outputs are connected to the first group of inputs of the adder, the second group of inputs which is connected to the outputs of the register, the control inputs of the generator and the register are connected to the outputs of the pulse distributor, which is distinguished by the fact that, in order to expand the function of the output voltage due to the conversion of the 1st dyuchgga t dda in dvibichnobychny and binary-ten 1 code in binary in the entire field of representation of real h sep, it contains the first register of the shift of the sum of the mat, the second register of the shift of the adder, an additional register, Overflow Correction block and encoder correcting iodine; vkbjfta which is connected to the outputs of the register, and the output is connected to the first group of inputs of the adder, the inputs of the second register TEDYM - SUMMATOR and four inputs of the young yykhray e of the first shift register. - SUMYATBRA; interconnected with correspondingly, u-. The secondary outputs of the adder, the output of the net./nrea from the senior {The discharge of the adder is connected to the input of the first digit of the first shift register of the adder, the serial input of the second register of the shift of the adder is connected to the first low register of the first register of the adder shift, the outputs of the first registrar of the adder are connected from the input of the register, the outputs of the SToiporo shift register of the adder are connected to the inputs of the additional register. TKj SSfSiMj-s i: -H ..  , -5 b 1ch & lchl 1, f output of which is connected to the second group of inputs of the adder, outputs of the three most significant bits of the additional register are connected to the first, second and third input of the overflow correction block, the fourth input of which is connected to the output of the CTapiuero discharge of the first register of the adder shift, and the outputs of the overflow correction block are connected to the first group of adder inputs, the auxiliary output of the overflow correction block is connected to the auxiliary input of the adder, control inputs of the encoder of the correction code, b The overflow correction lock, the registers of the accumulator and the additional register are connected to the outputs of the pulse distributor. Sources of information taken into account in the examination 1, USSR Copyright Certificate №228334, class., FOB 5/02, 1968. 2, Copyright Certificate SSS No. 543934, column С О Р Р 5/02, 1974. 3, USSR author's certificate in application number 2136416, c. 06 F 5/02, 1977 (prototype).