SU705695A1 - Asynchronous three-dimensional switching circuit - Google Patents

Description

(54) ASYNCHRONIC SPATIAL SWITCH

The invention relates to communication technology. I can be used in switching systems.

The asynchronous spatial switch is known, consisting of m groups with n input registers, the address output of each of which is connected to the input of the corresponding group decoder through the common for a group of input registers address bus and the information output of each of the input registers the line is connected to the corresponding input of all memory blocks and the output of each memory block is connected to the input of the corresponding output register 11.

However, this asynchronous spatial switch has low bandwidth.

The aim of the invention is to increase throughput.

To do this, an asynchronous spatial switch consisting of m groups with n input registers, the address output code of each of which is connected to the input trunk of the corresponding group decoder through the common for a group of input registers, and the information output of each of the input registers through a common for the group of input registers, the information highway is connected with the corresponding input of all the memory blocks and the output of each memory block is connected to the corresponding output register, m records are additionally entered si, m priority blocks and m read blocks, each i-th group of outputs (, 2, .., gp) of each group transmitter connected to the corresponding inputs of the i-th recording block, the control outputs of which are connected to the first control input the corresponding memory block, and the address output of the write block is connected through a serially connected priority block and a read block connected to the second control input of the corresponding n memory blocks (where n and m are integers, and m x n is the number of communication channels) .. 1Л ; G:,:,. , il, .3 i /; . , G ..,; 70 The drawing shows the structural:) electrical diagram of the device being predicated. An asynchronous spatial switch contains m groups with n input registers 1, group decoders 2, blocks 3 and 13 and output registers 4, as well as m recording blocks 5, m priority blocks 6 and m blocks; 7 hours off. The device works as follows. On the input address-informational matHCfjjanrtM in a pair of iroctynaer information, followed by the addresses of the output channels of the switching system, which is written to the input registers I. Addressing information4.4e words. arrive in blocks 3 of memory, and the addresses also arrive in the corresponding group decoders 2, which generate signals arriving in blocks 5 of the record. Each signal indicates from which group i (, 2 ..., m) of input registers 1 in which memory block 3 J (J 1,2 .. ,, n) the address-information word should be written. Record units 5 receive signals from all group deigafratores 2 and organize recording operations into the matrices of memory blocks 3 of address informational s, the corresponding signals of which 1. Since each 3 party block has m matrices, simultaneous servicing of all internal highways is achieved. devices. -V; :;:; :::.. :::::::::. Signals B., J equal to 1 are inserted by writing blocks 5 into corresponding blocks 6 prioritized, which are stored until the words are read from blocks 3 of memory. ,: -. . Thus, priority blocks 6 using signals B: I 1 drive the sequence .IJ to read words from the matrices of memory blocks 3 and output them to read blocks 7, which read the information-address words from the matrixes of memory blocks 3 and issue them them in the output registers 4. Type -fbiffaCnpefteiieHbt in accordance with the numbers ma ..RITCH- ,,.:.

Claims (1)

fxyi fj: -: a; f: K .- .. Thus, using the right-clicked device will provide an opportunity to increase the throughput capacity of an asymmetric spatial switch by m times, where m is the number of parallel and independently working internal highways of the device, which distinguishes it from prototype. Asynchronous space 1 switch consisting of m groups with n input registers, the address output of each of which through a common for a group of input registers address magistr p is connected with the input of the corresponding group decipher, and information output of each of the input registers through a common for a group of input registers the information highway is connected to the corresponding input of all the memory blocks and the output of each memory block is connected to the input of the corresponding output register, characterized in that in order to increase throughput. Additionally, m write blocks, m priority blocks and m read blocks, each i-th group of outputs (i 1, 2, ..., m) of each group descriptor are connected to the corresponding inputs of the | -th recording block, control outputs The cable is connected to the first control input of the corresponding memory booth, and the address output of the write block through the serially connected priority block and the readout module is connected to the second control input of the corresponding n memory blocks (where n and m are the goals of 1 Gsl and n x m - number of switched anal). Sources of information taken into account in the examination of the USSR Author's Certificate of the USSR No. 493037, cl. H 04 J C / BO, 1972 (prototype).