SU1656541A1 - Common memory direct access system - Google Patents

Abstract

The invention relates to computing and can be used to control multiple user access to shared memory. The purpose of the invention is to increase the system speed by multiplexing direct access to shared memory. The shared memory direct access system contains trunk 1, highway capture unit 2, data register 4, control block 6, buffer memory 14. shared memory 7, current address register 11, final address register 12, comparison circuit 13, adder 10. Due to the use of multiplexers of information and addresses, it is organized to store in the memory not only the arrays of subscriber information, but also the current and final addresses of the read or write array word for each subscriber. 2 hp f-ly, 5 ill. To subscriber

Description

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The invention relates to computing and can be used to build shared access systems for shared memory.

The purpose of the invention is to increase the system speed by multiplexing direct access to shared memory.

FIG. 1 shows a block diagram of a system of direct access to shared memory; in fig. 2 - the same. control unit; in fig. 3 - the same, block the capture line; in fig. 4, 5 - time diagrams of the system.

The system of direct access to the common memory (Fig. 1) contains a trunk 1, a block 2 for capturing a highway with n inputs of communication lines with subscribers 3 (n is the number of subscribers), a data register consisting of information register 4 and a register 5 , control unit 6, shared memory 7, information multiplexer 8, address multiplexer 9, adder 10, current address register 11, final address register 12, comparison circuit 13, buffer memory 14.

The block capture line (Fig.Z) contains a demultiplexer 15, multiplexer 16 and the device 17 priority.

The control unit (Fig. 2) contains a synchronization generator 18, a decoder 19, seven AND 20-26 logical elements, five OR 27-31 logical elements, an HE element 32.

The system works as follows.

The computer configures the shared memory access system, for which, via a trunk, records the starting and ending addresses for all subscribers in the shared memory, and the initial (current) address of the subscriber is recorded at the subscriber address, which is the subscriber sequence number and the final address is at the address whose low-order bits are equal to the subscriber's address. The upper 1st bit is set to 1 by the control unit.

For direct access to the shared memory, the subscriber sends his address through the block for capturing the main line, in the upper non-significant bits of which the characteristics of the type of work for the block 6 of control (reading, writing) and, if necessary, the information for writing are specified.

The address and information from trunk 1 is recorded in registers 4 of information and 5 addresses.

FIG. 4 shows a timing diagram of the operation of the control device,

FIG. 5 is a timing diagram of the signals of the sync pulse generator unit. The control unit 6 organizes access to the shared memory 7 in 4 clock cycles.

In the first cycle from memory 7 at

the subscriber reads the current (starting) address, and the 1st control input of the second group of the multiplexer 9 address is set by the control unit in O. This

The address is written to the current address register 11.

In the second cycle, the end address is read from the memory at the same address, only in the 1st bit of the control unit 6 is set 1. The end address is written to the end address register 12.

In case of coincidence of the current and final addresses, the comparison circuit outputs a control signal — a sign of the end of the array — to the control unit, which stops the exchange with the subscriber.

In the third cycle, at the subscriber's address, the modified

per current address, which is removed from the outputs of the adder 10 through information multiplexer 8.

In the fourth clock cycle at the current address, which is removed from register 11 of the current

addresses, through the address multiplexer 9, information is read from memory 7, which is written to the buffer memory and transmitted to the highway, or information is written from information register 4. The write or read mode is specified by the information management block at the highest non-significant bits of the address word sent by the subscriber. After receiving the next word, the subscriber either

confirms that the line is busy, or frees it for the work of other subscribers or computers.

The system provides direct access of any number of subscribers to shared memory,

at the same time, the volume of equipment practically does not depend on the number of subscribers (only the volume of shared access depends on it).

The system allows to achieve an increase in the service speed of any number of subscribers by organizing the storage of memory addresses in a shared memory.

Claims (2)

1. System of direct access to shared a memory comprising a line acquisition unit, a data register, a control unit, a current address register, an end address register, a comparison circuit, an adder, and a buffer memory, with the data register input through the trunk is connected to the main inputs-outputs of the block for capturing the line, the input of the array end of the control unit is connected to the same output of the comparison circuit, the first input of which is connected to the output of the end address register, and the second input and input of the adder is connected to the output of the current address register, control outputs data, the buffer memory, the current address of the control unit are connected to the corresponding inputs of the data register, the buffer memory and the current address register, respectively, characterized in that The goal is to increase system speed by multiplexing direct shared memory access, an information multiplexer and an address multiplexer are entered into it, the first and second inputs of the information multiplexer are connected to the output of the accumulator and the information output of the data register, respectively, and the output is the output of the system to the shared memory information input, the first address multiplexer address input is connected to the output of the current address register, and the second address input and the address input of the control unit connected to the address output of the data register, the output of the address multiplexer is the system output for connecting to the shared memory address input, the inputs of the current address register, the end address register and the buffer memory form the system input for connecting to the common memory output, the output of the buffer memory through the trunk is connected to the main inputs - the outputs of the block for capturing the trunk, the subscriber inputs and outputs of which are the inputs and outputs of the communication with the subscribers of the system, and the inputs of the station and the reset are inputs of the station and sat The dew from the system subscribers, the control input and the address control input of the address multiplexer, the information control information input of the information multiplexer, the control input address of the end address register of the destination address are connected to the corresponding outputs of the control unit whose memory management output is the common memory control input. 2. A pop-up system 1, characterized in that the control unit comprises a clock driver, a decoder, from the first to the seventh elements AND, from the first to the fifth elements OR, an element NOT, the first output of the clock generator of the sync pulses connected to the first input of the first element AND the output of which is connected to the first input of the first OR element, the output of which is connected to the data management output of the control unit, the second output of the imaging device is connected to the first input of the second AND element, the output of which is connected to the control output of the current The address of the control unit, the third output of the sync pulse generator is connected to the first input of the third element, And, the output of which is connected to the output of control0 the end address of the control unit and to the first input of the fourth element I. whose output is connected to the control output -, the control unit buffer, the fourth  the output of the sync pulse generator is connected to the second input of the first element AND, to the first input of the second element OR. the output of which is connected to the control output address of the control unit and to the second input of the second element AND, the fifth output of the sync pulse generator is connected to the second input of the second OR element, to the control output of the control unit and the second input of the third element And, the sixth output of the sync pulse generator is connected the first input of the third element OR, the output of which is connected to the second input of the fifth element AND, the output D of which is connected to the first input of the fifth OR element, the output of which is connected to the first input of the seventh AND element, the output of which is connected to the memory management output of the control unit, the seventh output 5 of the sync pulse generator is connected to the second input of the third element OR, to the second input of the fourth element AND, to the control information output of the control unit and to the first input of the sixth element AND whose output is connected to the second input of the fifth element OR, the address input of the control unit is the input of the decoder, the first output of which is connected to the first input of the fourth element 5 OR, the output of which is connected to the second input of the first element OR and to the first input of the fifth element AND, the second output of the decoder is connected to the second input of the fourth element OR and to the second input 0 of the sixth element AND, the output of which is connected to the second input of the fifth element OR, the input of the sign of the end of the array of the control unit is NOT connected to the second input of the seventh element I. 5z. System pop 1, different with in that the trunk acquisition unit contains a demultiplexer, a multiplexer, and a priority device, the subscriber inputs and outputs of the block being inputs the multiplexer and the demultiplexer outputs, respectively, are the priority priority devices, the outputs of which the inputs-outputs of the block are connected to the outputs of the multiplexer and to the inputs of the demultiplexer, the inputs of the quotation and reset of the type-5 block. are connected to the corresponding control inputs of the multiplexer and the simulation box .2. / Mv / tvfc connected to the corresponding inputs typlexer. connected to the corresponding control inputs of the multiplexer and demulfide JЈL. At &. R sw, UTA P ti5 CO-f P cos P CO 7 P . five Compiled by V.Sychev Editor A.Makovska Techred M. Morgantal b ° r -t-t R P P P P P P Corrector S.Cherni