KR100474715B1 - Data Rate Converters and Methods - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Speed conversion of communication systems

2. The technical problem to be solved by the invention

In a communication system, high speed data is converted into low speed and low speed data is converted into high speed data using a memory.

3. Summary of the Solution of the Invention

A first serial-parallel converter and a parallel-to-parallel converter for converting data of the first speed into second speed data, a second serial-to-parallel converter and a parallel-to-parallel converter for converting second speed data into first speed data, and the data A speed conversion device of a communication system having a memory for storing, stores the parallel data output from the first serial-parallel converter at the first write address location in the memory in the first conversion mode and stores the parallel data at the second read address location. The speed is converted by reading the stored data and outputting the data to the first serial-parallel converter, and storing parallel data output from the second serial-parallel converter in the memory at the second write address in the second conversion mode. The speed is converted by reading the data stored in the one lead address position and outputting the data to the second serial-to-parallel converter.

4. Important uses of the invention

Provided is a speed converter that can reduce the number of registers by storing the speed of data using a memory in a communication system.

Description

Data rate conversion device and method

The present invention relates to an apparatus and method for converting data rates in a communication system, and more particularly, to an apparatus and method capable of converting a rate of data using a memory.

In general, a communication system such as an exchange system and a transmission system is such that internal multiplexed data is interlocked with a low-speed communication system, and in this case, a rate adapter is required. The speed of the speed converter varies as needed. Here, we will look at an example of interlocking internal multiplexed data of 2.048Mbps with a system of 512Kbps. FIG. 1 is a diagram showing the configuration of a speed converter capable of changing a data line multiplexed at 512 Kbps to 2.048 Mbps into 512 K continuous data and vice versa. FIG. 2 is a serial / parallel converter in FIG. And timing for converting data in the parallel / serial converter.

In the speed converter having the configuration as shown in FIG. 1, serial to parallel converters 12 and 15 are received under the control of a time signal controller 11 when converting the continuous data into multiplexed data lines. The serial data is converted into parallel data, and the parallel to serial converters 14 and 13 store the data converted in parallel in the serial and serial converters 12 and 14 and output them under the control of the timing controller 11.

In case of converting 2.048 Mbps data into 512 Kbps data in FIG. 1, the serial / parallel converter 12 converts the received 2.048 Mbps data into parallel data as shown in FIG. The converted data is fetched and stored, and serially converted to 512 Kbps data under the control of the timing controller 11, and outputted as continuous data as shown in FIG. Serial-to-parallel converter 15 and parallel-to-parallel converter 13 perform the same method as described above when converting 512 Kbps data into 2.048 Mbps data.

In this case, the size of the register requires 128 when converting 2.048Mbps data into 512Kbps data and 128 when converting 512Kbps data into 2.048Mbps data. Therefore, when configuring the speed converter as shown in FIG. 1, a total of 256 registers are required.

As described above, in the case of using the conventional speed converter, when the continuous data is configured in the multiplexed frame, a multiple register of the number of frame bits is required. On the contrary, the format of the continuous data to the multiplexed frame requires a register cell that is double the number of bits. In addition, when the register cell is composed of individual devices, eight of them are the best in one device, and there is a problem in that they occupy a large area even when the ASIC is implemented.

It is therefore an object of the present invention to provide an apparatus and method which can convert the speed of data using a memory instead of a register in a communication system.

In order to achieve the objects of the present invention, an apparatus for converting a speed of data having a first speed and a second speed includes a first serial-parallel converter for converting serial data of a first speed into parallel data, and A first parallel serial converter for converting serial data of two speeds, a second serial and parallel converter for converting serial data of a second speed into parallel data, and a second parallel serial converter for converting parallel data into serial data of a first speed A first address generator for generating a first light address in the first period of the frame and a first lead address in the third period of the frame, and a second light address in the second period of the frame, And a second address generator for generating a second lead address in a fourth period of the frame, and generating a first conversion mode signal when converting first speed data into second speed data and converting the second speed data into a first speed. A control unit for generating a second conversion mode signal when converting the data, and storing parallel data output from the first serial-parallel converter at the first write address location when the first conversion mode signal is generated and stored in the second read address location. Reads the data and outputs the data to the first serial-parallel converter, and stores the parallel data output from the second serial-parallel converter at the second write address position when the second conversion mode signal is generated, and stores the data at the first read-address position. And a memory for reading data and outputting the data to the second serial-to-parallel converter.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the same parts in the figures represent the same reference signs wherever possible.

The speed converter of the present invention will be described assuming an example of converting from 2.048 Mbps to 512 Kbps, and conversely, converting from 512 Kbps to 2.048 Mbps. An example of converting from 2.048 Mbps to 512 Kbps is called a first speed conversion, and on the contrary, an example of converting from 512 Kbps to 2.048 Mbps is called a second speed conversion.

3 is a configuration diagram of a speed converter according to the present invention, in which a timing signal generator 31 includes / CS, / WR, and RD / 32 which are control signals of a memory 33 according to the speed of the speed converter. Generate a fetch clock of 38, and a parallel-serial converter 34,37. A first serial-to-parallel converter (2M / 512K serial to parallel converter) 32 fetches multiplexed 2.024 Mbps serial data, converts it into parallel data, and transmits the data to the data line of the memory 33. A first parallel serial converter 34 fetches parallel data output from the data line of the memory 33 and converts the speed into data of 512 Kbps. A second serial to parallel converter 38 fetches the multiplexed 512 Kbps serial data, converts the serial data into parallel data, and transmits the parallel data to the data line of the memory 33. A second parallel to serial converter 37 fetches the parallel data output from the data line of the memory 33, converts the speed into 2.048 Mbps, and outputs the converted data. A first address generator 35 divides a system clock output from the timing controller 11 to generate a first write address for writing data converted in parallel from the first serial-to-parallel converter 32 to the memory 33. At the same time, a first read address for converting the data written in the memory 33 in parallel by the second parallel serial converter 38 and outputting the data to the second parallel serial converter 37 is generated. A second address generator 36 divides a system clock output to the timing controller 11 to generate a second write address for writing data converted in parallel by the second serial-to-parallel converter 38 to the memory 33. At the same time, a second read address is generated for reading data written in the memory 33 in parallel by the first parallel serial converter 32 and outputting the data to the first serial parallel converter 34. The memory 33 records data output from the first serial-parallel converter 32 by a first write address output from the first address generator 35, and simultaneously writes data output by the second serial-parallel converter 38 by a first read address. Reads and outputs the data output from the second serial-to-parallel converter 38 by the second write address output from the second address generator 36 and simultaneously outputs the first serial-to-parallel converter 32 by the second read-address signal. Read and output the data recorded in. The memory 33 may use a static random access memory.

FIG. 4 illustrates a structure in which time sharing is performed to perform data write and read operations of the memory 33 in FIG.

The speed converter is used to communicate data between a high speed communication system and a low speed communication system. That is, the speed converter performs a function of converting high speed data into low speed data or converting low speed data into high speed data.

First, in a high-speed communication system, when a 512 Kbps of 64K bits are loaded in every 8K frame on a multiplexed 2.048 Mbps line, the first serial-to-parallel converter 32 composed of 8 bits divides the 64-bits into 8-bit units in parallel. Convert to data. The timing controller 31 generates the / WR and / CS signals of the memory 33 when the first serial-parallel converter 32 converts the data into parallel data, and the first address generator is configured to write the memory 33. 1 address is generated. Then, the memory 33 activates the chip select and write mode by the timing controller 11, and stores the parallel conversion data output from the first serial-to-parallel converter 32 in the area designated by the first write address. When the next frame is reached, the timing controller 31 outputs the / CS and / RD signals to the memory 33, and the second address generator 36 generates a second lead address. Then, the memory 33 reads out the corresponding data by the / CS, / RD signal and the second lead address and outputs the corresponding data to the first parallel serial converter 34. The first parallel serial converter 34 converts 2.048 Mbps data into serial data of 512 Kbps and outputs the converted data. The data conversion process as described above is a process of converting the data output from the high speed communication system to the data rate of the low speed communication system and outputting the same.

Contrary to the above, when 512Kpbs of continuous data is received in a low speed system,

The second serial-to-parallel converter 38 divides the 64-bit data into 8-bit units and converts the 64-bit data into parallel data. The timing controller 31 generates the / WR and / CS signals of the memory 33 when the second serial-to-parallel converter 38 converts the data into parallel data, and the second address generator is configured to write the memory 33 to the memory 33. 2 light addresses are generated. Then, the memory 33 activates the chip select and write mode by the timing controller 11, and stores the parallel conversion data output from the first serial-to-parallel converter 38 in the area designated by the second write address. In this case, the second write addresses supplied to the memory 33 may be stored in cells of eight memory 33 by one byte. The area stored in the memory 33 is bank-selected to the uppermost address of the memory 33 in order to avoid collisions with data of the fast multiplexer. When the next frame is reached, the timing controller 31 outputs the / CS and / RD signals to the memory 33, and the first address generator 35 generates the first lead address. Then, the memory 33 reads the corresponding data by the / CS, / RD signal and the first lead address and outputs the corresponding data to the second parallel-serial converter 37. The second parallel serial converter 37 converts 512 Kbps data into 2.048 Mbps serial data and outputs the converted data. The data conversion process as described above is a process of converting the data output from the low speed communication system to the data rate of the high speed communication system and outputting the data.

In the present invention, when data is written to and read from the memory 33, the write cycle is controlled twice and the read cycle is repeated twice. Therefore, the read and write operations of the memory 33 have a time sharing structure as shown in FIG.

That is, in the speed converter of the present invention, as shown in FIG. 4, one frame period is divided into four periods, and two periods of the first half are driven by the write period of the memory 33, and the other two periods of the second half are used as the read period. First, the first address generator 35 generates the first write address in the first period of one frame, and the timing controller 31 generates the / CS and / WR signals. Secondly, the memory 33 stores parallel converted data of a first speed output from the first serial-to-parallel converter 32. When the second period of one frame is reached, the second address generator 36 generates a second write address, and the timing controller 31 generates / CS and WR signals. The memory 33 stores the parallel conversion data of the second speed output from the second serial-to-parallel converter. Thirdly, when the third period of one frame is reached, the first address generator 35 generates the first lead address, and the timing controller 31 generates the / CS and / RD signals. The memory 33 reads the stored first parallel conversion data and outputs the first parallel conversion data to the first parallel converter 34. Fourth, when the fourth period of one frame is reached, the second address generator 36 generates the second lead address, and the timing controller 31 generates the / CS and / RD signals. Then, the second parallel conversion data stored in the memory 33 is read out and output to the second parallel serial converter 37.

As described above, in the case of configuring a speed converter in a system that communicates data at various speeds, it is not necessary to add registers by implementing the minimum registers and using the remaining storage cells as memory. For example, in the case of converting 2.048Mbps multiplexed data into 512Kbps continuous data, the speed converter of the present invention can be implemented as long as 32 registers and 128 bits (16 bytes * 8 bits) of memory cells. In addition, even when converting the speed converter from 2.048 Mbps multiplexed data to 1.024 Mbps continuous data, it is possible to implement 32 registers and 256 (32 bytes * 8 bits) memory cells. As can be seen from the above example, the speed converter of various speeds requires only a minimum increase in registers and memory cells, which eliminates the need for additional components in discrete components and reduces chip area in ASIC configurations. There is an advantage to that.

1 is a diagram showing the configuration of an apparatus for converting data rates in a conventional communication system.

2 is a view for explaining the conversion of data in FIG.

3 shows a configuration of an apparatus for converting data rates in accordance with the present invention in a data communication system.

4 is a diagram showing timing of accessing data in a memory in FIG.

Claims (2)

An apparatus for converting a speed of data having a first speed and a second speed, A first serial-parallel converter for converting serial data of a first speed into parallel data; A first parallel serial converter for converting parallel data into serial data at a second speed; A second serial-to-parallel converter for converting serial data of a second speed into parallel data; A second parallel serial converter for converting parallel data into serial data at a first speed; A first address generator generating a first write address in a first period of the frame and generating a first lead address in a third period of the frame; A second address generator generating a second write address in a second period of the frame and generating a second lead address in a fourth period of the frame; A control unit generating a first conversion mode signal when converting first speed data into second speed data, and generating a second conversion mode signal when converting the second speed data into first speed data; When the first conversion mode signal is generated, the parallel data output from the first serial-parallel converter is stored in the first write address position, the data stored in the second read-address position is read out, and output to the first serial-parallel converter. A memory for storing parallel data output from the second serial-parallel converter at the second write address position and reading the data stored at the first read-address position and outputting the data to the second serial-parallel converter when the second conversion mode signal is generated; Speed converter, characterized in that consisting of. A first serial-to-parallel converter for converting serial data at a first rate into parallel data, a first parallel-to-parallel converter for converting parallel data to serial data at a second rate, and serial data to a parallel data at a second rate; A data rate conversion method of a communication system, comprising: a second serial-to-parallel converter; a second parallel-to-parallel converter for converting parallel data into serial data of a first speed; and a memory for storing the data; Storing parallel converted data of a first speed output from the first serial-to-parallel converter in a first period of one frame in the memory; Storing parallel converted data of a second speed output from the second serial-to-parallel converter in a second period of one frame in the memory; Reading the first parallel conversion data stored in the memory at a third period of one frame and outputting the first parallel conversion data to the first parallel serial converter; And reading out the second parallel conversion data stored in the memory in a fourth period of one frame and outputting the second parallel conversion data to the second parallel serial converter.