KR970060772A - Data rate conversion apparatus and method - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

Speed conversion of communication system

2. Technical Challenges to be Solved by the Invention

The communication system converts the high-speed data to low-speed data and the low-speed data to high-speed data using the memory.

3. The point of the solution of the invention

A first serial-to-parallel converter and a parallel-to-serial converter for converting the data of the first rate into the second rate data, a second serial-to-parallel converter and the parallel-to-serial converter for converting the second rate data to the first rate data, Wherein the parallel data output from the first serial-to-parallel converter at the first write address position in the first conversion mode is stored in a memory, and the parallel data output from the first serial-to- Wherein the parallel data output from the second serial-to-parallel converter is stored in the memory at the second write address position in the second conversion mode, and the parallel data output from the first serial- Reads the data stored in one read address position, and outputs the read data to the second serial-to-parallel converter to convert the speed.

4. Important Uses of the Invention

A communication system is provided with a speed conversion device capable of reducing the number of registers by storing the speed of data using a memory.

Description

Data rate conversion apparatus and method

Since this is a trivial issue, I did not include the contents of the text.

3 shows a configuration of an apparatus for converting a data rate according to the present invention in a data communication system; Fig.

4 shows the timing of accessing data in the memory in Fig. 3; Fig.

Claims (2)

An apparatus for converting a speed of data having a first speed and a second speed, the apparatus comprising: a first serial-to-parallel converter for converting serial data of a first rate into parallel data; A second serial-to-parallel converter for converting serial data of a second rate to parallel data, a second parallel-to-serial converter for converting the parallel data to serial data of a first rate, A first address generator for generating a first read address, a second address generator for generating a second write address and a second read address, and a second conversion circuit for generating a first conversion mode signal when converting the first speed data to second speed data A control unit for generating a second conversion mode signal when the second speed data is converted to a second speed, and a controller for generating a second conversion mode signal when the first conversion mode signal is generated, And outputs the data stored in the second read address position to the first serializer and outputs the read data to the first serializer when the second conversion mode signal is generated, And a memory for storing parallel data and reading the data stored in the first read address position and outputting the read data to the second serial-to-parallel converter. A first serial-to-parallel converter and a parallel-to-serial converter for converting data of a first rate into second rate data, a second serial-to-parallel converter and a parallel-to-serial converter for converting the second rate data to first rate data, Storing parallel conversion data of a first rate outputted from the first serializer in a first period of one frame in the memory, Storing parallel conversion data of a second rate outputted from the second serializer in a second period in the memory, reading the first parallel-converted data stored in the memory in a third period of one frame, And outputting the second parallel-converted data stored in the memory in a fourth period of one frame to the second parallel-to-serial converter Speed converting method characterized by made of an. ※ Note: It is disclosed by the contents of the first application.