KR950004745A

KR950004745A - Analog data sample and storage circuit

Info

Publication number: KR950004745A
Application number: KR1019930013513A
Authority: KR
Inventors: 권오상
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1993-07-16
Filing date: 1993-07-16
Publication date: 1995-02-18

Abstract

본 발명은 아날로그 데이타 샘플 및 저장회로에 있어서 저속의 디바이스로도 고속의 데이타 처리를 실현 할 수 있도록 하기 위한 것으로, 입력되는 아날로그 데이타를 클럭신호에 동기되어 샘플링한 다음 디지탈 데이타로 변환하여 메모리수단에 기록하고, 클럭신호에 동기되어 입력되는 모드 제어신호에 상응하는 어드레스 신호를 메모리수단에 출력함으로써, 디지탈 데이타를 메모리수단에 기록하거나 기록된 디지탈 데이타를 판독하여 출력하는 아날로그 데이타 샘플 및 저장회로에 있어서, 아날로그 데이타를 디지탈 데이타로 변환하는 A/D 변환수단과 A/D 변환된 디지탈 데이타를 기록하는 메모리수단을 병렬접속된 복수의 A/D 변환기 및 복수의 메모리로 각각 구성한 것이다.The present invention is intended to realize high-speed data processing even with a low-speed device in an analog data sample and storage circuit. The analog data input is sampled in synchronization with a clock signal, and then converted into digital data and stored in the memory means. In the analog data sample and storage circuit which writes and outputs an address signal corresponding to a mode control signal input in synchronization with a clock signal to the memory means, thereby writing digital data to the memory means or reading and outputting the recorded digital data. A / D conversion means for converting analog data into digital data and a memory means for recording A / D converted digital data are respectively composed of a plurality of A / D converters and a plurality of memories connected in parallel.

Description

Analog data sample and storage circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 아날로그 데이타 샘플 및 저장회로의 블럭구성도, 제 2 도는 본 발명에 따른 아날로그 데이타 샘플 및 저장회로에 있어서 기록 모드시의 타이밍도.1 is a block diagram of an analog data sample and storage circuit according to the present invention, and FIG. 2 is a timing diagram in a write mode in the analog data sample and storage circuit according to the present invention.

Claims

The analog data inputted is sampled in synchronization with a clock signal, converted into digital data, recorded in memory means, and outputted to the memory means by outputting an address signal corresponding to a mode control signal input in synchronization with the clock signal. An analog data sample and storage circuit which writes data to the memory means or reads and writes recorded digital data, comprising: a plurality of A / D conversion means for converting the analog data into digital data and the memory means connected in parallel; An analog data sample and storage circuit, each comprising an A / D converter and a plurality of memories.

The analog data sample and storage circuit according to claim 1, wherein the circuit further comprises dividing means for dividing the clock signal into a number of different clock signals corresponding to the plurality of A / D converters.

3. The circuit according to claim 1 or 2, wherein the circuit comprises an address generator for generating the address signal, which is synchronized with the timing of the output data of the A / D conversion means when the mode control signal is a write mode signal. And a read address in parallel when the mode control signal is a read mode signal.

※ Note: The disclosure is based on the initial application.