SU942139A1 - Buffer storage device - Google Patents

Description

C5 BUFFER. STORAGE DEVICE

one

The invention relates to a technique of data transmission systems and can be used in message switching centers.

Known buffer storage

a device (RAM) that can be used to accumulate and intermediately store messages that are meaningful data blocks. The device contains a control unit j pulse generator, input register, AND elements, RAM memory, output register, read and write address counters, OR element and is the address decoder P.

A disadvantage of the known device is its complexity.

The closest to the proposed technical entity is 20 BZU, containing the input word register, input elements AND, address counters, address decoder, memory matrices, OR elements, output fishing register and control node. The source of messages accompanies the input words with the clock pulses of the ZP record. If the first memory matrix is free. This is recorded. The input word is written to the input word register. The control signal, which arrives at the control inputs of the first input elements And, allows overwriting the contents of the register of the input word into the first memory matrix.

After filling in the first memory matrix, the control node generates a busy signal, notifying the receiver of messages about the presence in the BZU of the message. At the same time, a record arrives at the input of the BZU of the new message in the second memory matrix, if it is free. The control signal, which arrives at the control inputs of the second input elements And, allows overwriting the contents of the input word register into the second memory matrix. Sequential sampling of addresses of memory matrices is carried out using address counters and address decoders. The information is read from the BDU when a message is received from the receiver of sync pulses. The control signal, which arrives at the control inputs of the first output elements AND, permits the passage of a word from the second memory matrix to the elements OR to the inputs of the output word register. If the message receiver responds to the busy signal in a timely manner, writing to the RAM is performed almost continuously due to the sequential release of the memory array. In the successful case, the RAM is completely filled and the control node generates a signal informing that further recording of messages in the RAM is impossible. In the communication process, information distortions (failures) may occur in the messages. The methods of detecting and correcting both single and group failures of the text part of a message are quite well known. However, synchronization failures are possible, leading to a distortion of the structure and even the format of the message. Their recovery in the process of processing in real time is practically not possible. A characteristic feature of such failures is the lack of a code message in the last word: a combination of the end of message marker 2. A disadvantage of the known device is the possibility of accumulating and transmitting non-recoverable failed messages for processing. In addition, the device stores the code combination of the last word of the message, which is fixed for all messages, which leads to an increase in equipment and a decrease in the reliability of readable messages. So, for example, as a result, a message may be removed from the processing in the last cell of any of the memory matrixes of the BZU. The purpose of the invention is simplification. devices and improved read accuracy. The goal is achieved by the fact that in the buffer storage device containing the first and second drives, the information inputs of which are connected to the outputs of the And elements of the first and second groups, the address inputs of the first and second drives are connected to the outputs of the first and second decoders, respectively, the control inputs connected to the corresponding outputs of the control unit; information inputs of the first and second decoders are connected to the outputs of the first and second counters, respectively inputs of which are connected to the corresponding outputs. control unit, information outputs of the nerve and second drives are connected to the same inputs of the AND elements of the third and fourth groups, each other inputs of which are connected to the corresponding outputs of the control unit, the outputs of the AND elements of the third group are connected to the same inputs of the OR elements, the other inputs of which are connected to the outputs of elements AND of the fourth group, one inputs of elements AND of the first and second groups are connected to the outputs of the first register, the control input of which is connected to the corresponding output of the control unit The lazy, other inputs of the elements of the first and second groups are connected to the corresponding outputs of the control unit, the outputs of the elements of the OR group are connected to the information inputs of the second register, the first control input of which is connected to the corresponding output of the control unit, a third decoder and element 2I-OR, some of the inputs are connected to the corresponding outputs of the first and second decoders, and the other inputs are connected to the corresponding outputs of the control unit, the output of the 2I-OR element is connected to the second control th input of the second register, a third decoder inputs connected to the outputs of the first register, the third output of the decoder and the respective outputs of the first and second decoders connected to the inputs of the control unit. The drawing shows the block diagram of the device. The buffer storage device contains the register 1 of the input word, the elements AND 2 of the first group, the elements AND 3 of the second group, the first counter, the first decoder 5, the first accumulator 6, the second drive 7, the second decoder 8, the second counter 9, the elements 10 of the third groups, elements AND 11 of the fourth group, group of elements OR 12, output word register 13. Control block k, third decoder 15, element 16. The message words, accompanied by synchronization pulses of the EA record, arrive in parallel-serial from the source of messages to the information inputs of the reg Stra 1 input word. The control unit AND generates from the sync pulses of the RFP signals UO, U1, UZ, if the recording is made to the collector 6, or signals from the UO, U2, UA, if the recording is made in a drive 7. By the signal of the OA, the input slle is written to register 1. Signal U1 permits copying of the input word from register 1 to drive b, and signal У2.- to drive 7. Sequential sampling of addresses of drives 6 and 7 is carried out, respectively, using counters 4, and decoders 5 and 8. Address sampling is resolved by Si1- Knock UZ for drive 6 and signal y for drive 7. Change The state of counter 4 is carried out on the trailing edge of the ultrasonic signal, and the counter 9 - on the trailing edge of the signal Y. Each state of any of the counters corresponds to a certain cell of the associated memory matrix except for the last state, since the cell for the last word no messages in memory matrices. Thus, the last word of the message is not recorded in the LPU. When writing to the register 1 of the input word containing the coding combination of the end of message marker, the decoder 15 generates the signal of the ISS, which enters the control unit I. The coincidence of the ISS signal with the corresponding of the A1 signals generated by the decoders 5 and 8 when recording information indicates the presence of the end marker code combination in the next message byte and causes the appearance of a potential occupancy signal 1.1 at the output of the control signal 14. in BZU message. The signal Zl is present at the output of the BZU as long as there is at least one message in the BZU. After filling in both memory matrices, the BZU generates a signal 2. 2 notifying that the recording of messages in the BZU is impossible. If, as a result of a failure in the message being written to the memory matrix, there is no word with the code pattern of the end of message marker, then after the recording is completed, this memory matrix is considered to be empty. In this case, the LPD does not generate a signal Z 1 if the other memory matrix is free, as well as the signal Z2 if the other memory matrix is full. Thus, at the BZU input, the messages with the distorted structure or format are eliminated. The reading of the message words from the BDB is carried out by the C4 clock pulses from the message receiver. In this case, the control unit 14 generates the sync pulses UZ, U5, U7 from the sync pulses during the reading of the message from the accumulator 7. The signal U7 records the output word in the register 13. If any of the counters 4 and 9 working for the reading is in the last state At the output Ai of the corresponding decoder, a signal appears, the passage of which to the register setup input is resolved 13 times by the signal У5 when reading a message from accumulator 6, and by signal UB - when reading the message from the accumulator 7. ovochny input register 13 provides the appearance at its outputs a codeword end marker message. The invention allows to increase the reliability of the last word read in the message by eliminating the possibility of failures in the process of writing and storing this word in the RAM, and at the same time simplifying the design of the RAM, reducing the number of cells in each memory matrix, since it is not necessary to write and store the word containing fixed code combination. In addition, information is excluded from the flow of information passing through BZU 79

communication with a distorted structure or format.

Claims (2)

1. USSR author's certificate number 51515, cl. ATP 9/00, 197. 2.On two-operation buffer Instrumentation. Publishing house of the Leningrad Institute of Fine Mechanics and Optics, Leningrad, №, 197 (prototype).