SU556480A1 - Device for receiving information with error detection - Google Patents

Description

one

The invention relates to automation and the transmission of diffracted data and can be used in iifOmashionnyh systems for displaying digital information on (Lreem distribution points.

Devices are known for transmitting and receiving information HI with temporarily sealing the communication channels. To maintain the synchronization and synchronicity of the transmitting and receiving distributors, they use high-stability generators and complex circuit-based and frame synchronization 1.

Also, devices for receiving and shaping are contained, containing a distributor, a diverter, a ron1GZ impulse, a generator of pulses, a memory block, and And 2 elements, as well as a device that uses / continuous cyclic ogres. devices do not detect errors in received information, and receiving valves must have the same number of elements as transmitters.

It is also known a device for receiving information that performs sequential processing of the received information and contains a pulse generator, a phasing unit, a serial code-to-parallel converter, a memory unit, an error detection node, comparison elements and

elements And 4. However, this device is cumbersome in the case of its technical implementation for receiving a large volume of transmitted messages.

The closest to the proposed technical solution is a device for receiving information with error detection, containing a phasing unit, the first input of which and the first input of the first element AND

connected to the input of the device, the left. output of the phasing unit is connected to the second input of the first element I, the output of which is connected to the input of the serial code transducer in-parallel, whose information outputs are connected to the corresponding inputs of the memory block, allowing the inputs of which are connected to the outputs of the information element cops, whose ler-in inputs are connected to the output of the switch, the decoder, and the elements OR and AND 5.

However, the known device does not provide sufficient reliability of reception when transmitting to the item of a large number of messages.

The purpose of the invention is to increase the reliability of receiving large amounts of information from a central point through a one-way communication channel.

This is achieved by the fact that

device entered binary group counters

information, and binary bit counters of the INFORMAssh bits, additional elements AND, a code comparison unit and an error detection unit, the first output of which is connected to the second (INPUT of the phasing unit and to the control input of the memory unit, the second output is connected to the second inputs and informational elements And, the first control output of the sequential code to parallel converter is connected to the first output of the bending box and to the control inputs of the decoder and code expansion block, the second control output of the converter of a sequential code in parallel is connected to a counting input-1 binary counter of information bits, the third control output is connected to the first input of the second element I and to the second input of the bending detection unit, the fourth control output is connected to the first input of the third element I and to the third input the error detection unit, the second output of the phasing unit is connected to the fourth input of the one detection unit, to the reset input of the binary counter of the information block, and to the first input of the OR element, the third output of the phase unit It is not connected to the reset input of the dBOic information group counter, the output of the third element And directly and through the binary counter of the groups and the information is connected to the corresponding inputs of the fourth element And, the output of the second element And directly and through the binary counter of information blocks It is connected to the corresponding inputs And, the outputs of the binary counter of information groups, the binary counter of blocks of information, and the binary counter of information bits are connected to the inputs of the switch, the information outputs of serializer code parallel and combined same outputs of the fourth and fifth AND elements are connected to the corresponding inputs of the code comparison unit, the output of which is connected to the second input of the OR element and the fifth input of the error detection unit, the output of the OR element is connected to the reset input of the binary counter information bits, the outputs of which through the decoder are connected respectively to the third input of the phasing unit and to the second inputs of the second and third elements I.

The drawing shows the structural scheme of the prerequisite.

The device contains a serial code to parallel converter 1, an AND 2 element, a 3-phase block, binary information group counters, information blocks, 4, 5 and 6 information bits, And 7 and 8 elements, a decoder 9, And 10 and II, element OR 12, code comparison unit 13., Error detection unit 14, co; mmutator, 15, information elements 16i-16 ;, memory block 17 (18-21 - control outputs of converter I; 22i-224 - its information outputs; 23i-23 ;; - binary code 4 code outputs of information; - binary 5 code code outputs of the block information; 25i-264 - code binary counter outputs 6 bits of information rows).

The operation of the device is as follows.

On the device in the course of a one-way connection. information is received, containing information sources, the full volume of which is divided into tons of soil, each block of information is divided into k blocks, each block contains bits (signs). The whole amount of information, consisting of m-ft- / bits, is transmitted sequentially, bitwise during one complete cycle, into a one-way SVEZI channel, and the cycles are repeated continuously. Speed leredachi. ok

type of communication channel and allowable waiting time. In one complete cycle, the input of the device receives m address combinations. Numbers of groups, m – k address combinations of numbers, blocks, and ph phasing;

The start of the cycle and one phasing combination End of the cycle. All combinations, both informational and addressable and phased, are transmitted by a twofold seven-element code, for example, by the start-stop method.

The code part of each combination consists of four information elements, two elements of the prize. On a group or block and. Element addition to parity. To these seven elements, the start-up and stapling phasing elements are added.

In the course of the transfer, the bits of the first group are sequentially polled, then the second, and so on, in order of increasing their numbers.

The transfer cycle begins with the transfer of the cycle number, for example, consisting of eight "zeros, including the start one. A two-wire communication line connecting the central point to

By the receiving point, it is fed to the input of the 3 phase unit. It counts the number of "zeros following one after another, and if they arrive exactly eight times more, it gives out one output a potential signal, an opening element I 2, and another output - a pulse signal that sets up the initial states counter and 5 and 6. Counter 4 is reset with the signal "End of previous cycle. Next

A combination of the number of the first group is received, which will look like “0010001. Here, the first four elements, counted on the right, represent the binary image of the decimal number 1, meaning the number of the first block, and the unit of the fifth element carries in itself the sign that the transmitted combination is addressable and group address transmitted. After the converter has received this combination at the information outputs

22i-224 will be set to the time equal to the stop stop length, the combination "0001, cTaipTOBbift impulse from output 19 takes up the unit in counter 6, and the impulse corresponding to the unit of the fifth element of the combination will exit from output 21. element travel, AND 10. Decoding of the states of counter 6 is carried out by a desphaser 9. If the combination of the beginning of the first cycle should arrive at the combination of the group number, is made by the connection — the first output of the decoder 9 with the second input of the element 10 Therefore, if counter 6 is in uu "0001, the AND gate 10 is opened and the pulse output from counter 21 will establish 4 .v state" 0001, and AND gate 7 opens.

Thus, on the two inputs of block 13 comparison of codes, code combinations are set-in: “0001, acting on outputs 22i-22, and“ 0001, acting on outputs 23i-23l of counter 4. Impulse, confirming the parity by that key (binning, output 18 is supplied to the storing input of the comparison unit 13, which verifies the identity of the codes, and if they are not identical at its output: they do not appear, thanks to which the error detection unit 14 generates a signal "Snapshot returning the phasing unit 3 initial state, at which time the If the codes are identical and the combination is even, the converter starts another combination with the number of the first block of the first group and has the form "0100001. Here, the first four elements, counted on the right, represent the binary ibid ( The decimal number is "1", meaning the number of the first block, and "one in the sixth element means the sign of the block number. At the outputs, the combination" 0001 is set again, "one is added to the counter, the signal from its second output is opened NT 11 and output 20 is recorded "unit in the count 5, which is set to the state" 0001. The code equalization unit 13 checks, as in the previous case, the code state of the counter 5 and the code arriving at the outputs 22i-22l. In the case of identical codes at the output of the code comparison unit 13, an impulse appears confirming the correctness of the reception of this address combination and, through the OR 12 element, setting to the initial state of the Dual counter meter 6. After this, the information combinations of the first bits begin to arrive a block of the first group, each of which is checked for parity and via outputs 22, -224, is transmitted to memory block 17 and is accompanied by a clock signal generated by error detection block 14.

After receiving the bits of the first block to the input of the converter 1, the combination number of the second block “0100010. After it pr. Byema, counter 6 is set to (/ +

-) - 1) -th state (/ is the number of bits in a block). From the (+1) output of the decoder 9, a signal arrives, which opens element 11, so that from its output to the input of binary counter 5 it receives an implant that translates it into the state "0010. Thereafter, the code comparison unit 13 compares the code at the outputs 24i-244 of counter 5 and the code at the outputs in the order described, after which

the binary counter 5 is reset again and the reception of the bits of the second block, etc., starts.

After receiving the bits / g-th block in the first group receives a combination of numbers

the second group, then in the same order the address and informational combinations related to this group.

The switch 15 selects the desired GROUP and unit. is he

connected to the outputs of binary counters 4, 5 and 6 23, -23 l, 24, -24 d and 25, -25.,. In the length of time. during which the combinations of the selected block are received, alternately, in the order of arrival of the bits of this block, AND 16i-16- elements are prepared, and at the moments of arrival, their combined second sync signal inputs to the corresponding cell of the memory block 17 are recorded. arriving on exits 22, -

22 ....

After the transfer of all / bits of the last fe-ro block of the last / nth-th band, the transfer is performed (the binning bin count is "End of the cycle. At (/ + P-M output of the decoder 9

a signal should appear allowing the reception of this combination, consisting of a number. out of eight units, including stop units, with a 3 phase unit. After its reception, the binary counter 4 is restored to the initial state, and the next combination of the "Start of the cycle is reset to the initial states of binary counters 5 and 6, after which the operation in the next cycle continues in a similar way.

If any bending is detected — in the address or information format — the input of the Transformer of the 1 is closed by the signal M from the block 3. Phasing, and the block 14 of the detection of the beacon gives a signal to erase

which erases information in memory block 17.

The proposed facility has improved economic and operational characteristics; when using the device, communication channels are simplified, the accuracy of receiving information and the mobility of the device increase.

Claims (5)

1. Emel Nov. A. A. and others. Frequency telecontrol. M., “Svy, 1966, p. 163-170. 2. Tztevich V. N. Osnovy telemekhaniki. M.-L., “Energie, 1967, p. 69, fig. 6-2. 3. In the same place 73, fig. 6-3. 4. Urgeison R.I. Pomekhustoychivno; st Digital systems for the transmission of telemechanical information. L., “Energie, 1971, p. 185-186, fig. 6-3. 5.Tutevich V.N. Telemechanika. M., 1973, €. 329-331. 23, 23s23 2t, Zt22t32 2Sf2S22S3252f Jx six si N1 Jx six six sLx Jx six NJ 1B € 17