SU1234990A1 - Device for transmission and reception of digital information - Google Patents

Abstract

This invention relates to a technique for transmitting digital information over wired communication lines, and may be. used in remote control systems for transmitting commands and messages. The amount of information transmitted increases. The device contains a transmitting side 1 consisting of information sources 2, multiplexer 3, counter 4, key 5, clock generator 6, one-oscillator 7, AND-OR-HE element 8, AND 9 element and transmitter 10, line connection 11 and the receiving side 12, consisting of the receiver 13, the sync pulse allocation unit (VVS) 14, the shift register (PC) 5, the AND 16–19 elements, two triggers (T) 20 and 21 of the counter 22, the decoder 23 and the memory register 24. From the output of the transmitter 10 through the communication line 11 to the receiver I3 signals are received in the form of a bipolar quasitroic code but. The receiver 13 receives these signals, restores their shape and amplitude, and converts into two sequences of unipolar rectangular pulses, one of which arrives at PC 15 and the other at BBS 14 and T 21. Using PC 15, signals are generated that provide phasing counter 22 and T 20. The signal from the inverse output T 20 permits or prohibits the recording of information from the decoder 23 into the memory register 24. 1 cp f-crystals, 4 Il. with to (L rs5 oo 4: s CO CO

Description

"

The invention relates to a technique for transmitting digital information over wired communication lines and can be used in remote control systems for transmitting commands and communicating

SRI.

The purpose of the invention is to increase the amount of information transmitted.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - block diagram of the transmitter; in fig. 3 and 4 - timing charts of the transmitting and receiving side.

The device for transmitting and receiving digital information contains a transmitting side 1 consisting of sources of information 2, multiplexer 3, counter 4, key 5, generator 6 clock pulses, single vibrator 7, element ti -.- linH-HE 8, element I 9, transmitter 10, communication line 11, receiving side 12, consisting of receiver 13, clock extracting unit 14, shift register 15, fourth element 16, second and third elements 17 and 18, first element 19, first trigger 20, of the second trigger 21, - counter 22, decoder 23, memory register 24, and transmitters are 10 consists of first and second registers 25 and 26 shift the first, second, third, fourth and fifth AND gates 27-31, the delay element 32, a trigger 33, OR gate 34, the output transformer 35.

The device works as follows.

When the device is turned on at the transmitting side 1, the counter 4 is set to the state in which O is present at its outputs, while the outputs of multiplexer 3 are connected to its front entrance where O is always present. This state is initial for the operation of the device. Logic O levels from counter 4 additional 10

It also arrives at the element AND-ILIDA 8, which only in this state of counter 4 and multiplexer 3 gives the resolving signal. The signal from element AND 9 is fed to the second input of transmitter 10 (Fig.Zo) and to the start of the one-shot 7. The signal of a certain duration from the one-shot 7 goes to the key 5, which is closed. In this case the clock im12349902

Pulses from the generator 6 clock pulses in the counter 4 are not received. After the termination of the signal of the one-shot 7, the key 5 opens and the clock pulses arrive at the counter 4, which, changing its state, switches the inputs of the multiplexer 3 to the following inputs. The signals from the inverse output of the multiplexer 3 and the generator output 6 from the clock pulses are received respectively at the first (FIG. 3) and third (FIG. 3c) inputs of the transmitter 10, with the signals from the inverse output 1 of the multiplexer 3

J5 correspond to the signals from the sources of information 2. The signals of the first and second inputs of the transmitter 10 are received respectively at one of the inputs of registers 25 and 26, to other inputs

20 of which receive clock pulses from the third input of the transmitter 10.

Registers 25 and 26 are two-bit registers that convert the postage code into parallel. From the outputs of the 1st and 2nd bits of the register 25, the signals arrive at the first inputs of the elements 27 and 28, the second inputs of which receive clock pulses from the third input of the transmitter 10. At the outputs of the elements 27 and 28 pulses are formed (Fig. 32 , 4), then arriving at the inputs of the OR 34 element. The signal from the output of the AND 25 element also enters the 5th input of the trigger 33 and carries out its phasing (Fig.33 o).

The OR element 34 provides for the formation of a synchrotransfer, which is a mating combination in the form of a two-bit pulse code sequence, which is used for the cycle synchronization of the trigger 20 and the counter 22 at the reception: th side 12. The information signals from the output of the 2nd bit of the register 26 (FIG. .E) arrive at the first input of the element I 29, the second input of which receives the clock pulses: from the third input of the transmitter 10. From the output of the element 29 and the informative signals (fig.3l) arrive at the input of the delay element 32 and - the input of the trigger 33, which operates in the counting mode, and from its direct and inverse outputs, pulses are removed (FIG. Ze, and), are sent to the first inputs of the elements 31 and 30, respectively, to the second inputs of which from the exit ele30

35

40

The delay element 32 has positive information pulses. From the output of the AND 31 element (Fig.Zk) the even information pulses arrive at the third input of the OR 34 element, from the output of which then is fed to one input an output transformer 35, to another input from the AND 30 element (Fig .3 odd information pulses are fed in. Using the output transformer, two sequences of unipolar pulses are converted into a bipolar quasi-trivial code (Fig. 3 / m), coming from the secondary winding of the output transformer 35 n Transmitter output 10 and then to the communication line 11, and from the transformed sequences transmitted in the positive polarity and the other in a gel negative.

From the communication line 11, signals 13 are received at the receiver 13 in the form of a bipolar quasitroic code (Fig. 4a). Receiver 13 provides for receiving signals from communication line 11, restoring the shape and amplitude of signals and converting them into two sequences of unipolar rectangular pulses (Fig. 46b), one of which corresponds to positive input signals, and the other is the sum of positive and negative input signals. From the first and second output of the receiver 13, the indicated pulse sequences are fed respectively to the input of the sync signal extraction unit 14 to the D input of the trigger 2 and the input of the three-bit shift register 15. The sync signal isolation unit 14 is a phase locked loop and produces synchronous and in-phase clocks with the signals. coming from the communication line. The sync signal extraction unit 14 is essentially an astatic control system, in which the magnitude of the steady state phase mismatch of the pulse in the And 19 element must coincide signals from counter 22 and the decoder 23. With this coincidence, the signal from the output of the And 19 element (Fig. 4h) arrives

neither depends on the initial detuning of the generators on the transmitting and receiving-50 on the S input of the trigger 20, which is set to another state

Noah sides 1 and 12.

During operation, the phase and frequency of the controlled oscillator are automatically adjusted, at which the frequency difference and phase mismatch error become close to zero, which leads to an increase in the permissible interruption without (fig.4g) and generates a signal to enable the display of digital information from the register 24 memories. The signal from the inverted output of trigger 20 prohibits the recording of information from the decoder 23 into the memory register 24. The subsequent operation is repeated cyclically.

0

the synchronization turn, since the phase difference will be due only to the random component instability of the generators.

five.

From the sync allocation unit 14, the clock pulse sequence (Fig. 4d) receives the shift register 15, the trigger 21, the elements AND 17 0 and 18, the counter 22 and the element 16, which also receives signals from the output of the trigger 21. With the help of the register 15 and elements 17 and 18, the inputs of which are connected to the corresponding outputs of the shift register 15, signals are generated that ensure the phasing of the operation of the counter 22 and the trigger 20, and the signal c. the output element And 17 (Fig.4O) is fed to the counter 22, and the signal from the output of the element And 18 (Fig.4e) is fed to the trigger 20. Using a signal from the inverse output of the trigger 20 (Fig. 45), enter; its input Element I 16, provides for the strobing of information signals (Fig. 4 ()). The signal from the inverse output of the trigger 20 p. s. also blunt on one input of the memory register 24 and allows writing information from the decoder 23 into it. From the direct output of the trigger 20 (Fig. 4g), it enters another input of the register 24 of the memory and prohibits the indication of the result. The signals from the outputs of the counter 22 (Fig. 4k, l, m) are fed to the inputs of the decoder 23 and the inputs of the element I 19, to the inverse input of which a signal is sent from the last output of the decoder 23. With the device working correctly, the signal from the latest output of the decoder 23 has the level O, since the last input of the multiplexer 3 is always O. After the transmission of the last (strictly specified in number) pulse in the And 19 element, the signals from counter 22 and the decoder 23 must coincide. With this coincidence, the signal from the output of the And 19 element (fi 4n) arrives

0

0 to the S input of the trigger 20, which is set to another state

(Fig. 4g) and generates a signal for enabling the display of digital information from the memory register 24. The signal from the inverse output of the trigger 20 prohibits the recording of information from the decoder 23 into the memory register 24. The subsequent operation is repeated cyclically.

Claims (2)

1. An apparatus for transmitting and receiving digital information, comprising, on the transmitter side, a clock pulse, the output of which is connected to the first input of the key, the output of which is connected to the input of the counter, the outputs of which are connected to one the multiplexer inputs and inputs of the AND-OR-NOT element whose output is connected to the first input of the element AND whose output through the one-vibrator is connected to the second key input, the outputs of information sources are connected to other inputs of the multiplexer, one output of which is connected to the first input of the transmitter, at the receiving to the receiver’s side, the first output of which is connected to the input of the clock selection unit, the direct and inverse outputs of the first trigger are connected to the inputs of the memory register, the counter outputs are connected to the corresponding inputs decoder, the first output of the counter is connected to the first input of the first element And, the second input of which is connected to one of the outputs of the decoder, the outputs of which are connected to the inputs of the memory register, the second and third elements And, with In order to increase the amount of information transmitted, on the transmitting side the output of the clock generator is connected to the second input of the transmitter, the third input of which is connected to the output of the element I, the second input of which is connected to another output of the multiplexer, is entered at the receiving side the shift register, the second trigger and the fourth element And, the second output of the receiver is connected to the first input of the shift register, the first and second outputs of which are connected respectively to the first inputs of the second and third elements And, the second inputs of which are combined and connected to the third output of the shift register, output The sync pulse allocation unit is connected to the second input of the shift register, the third input of the second element AND, the first inputs of the second trigger, the counter and the fourth | Q j o s 0 five 0 In addition, the output of which is connected to the corresponding input of the receiver, the first output of the receiver is connected to the second input of the second trigger, the output of which is connected to the second input of the fourth element, the third input of which is connected to the inverse output of the first trigger, the S input of which is connected with the output of the first element I, the output of the second element I is connected to the second input of the counter, the output of the third element I is connected to the R input of the first trigger, the last output of the counter is connected to the third input of the first element I. 2. The device pop. 1, which differs from the fact that the transmitter consists of two shift registers, five AND elements, a delay element, a trigger, an OR element and an output transformer, the first inputs of the first and second shift registers being the first and second inputs of the transmitter, the second inputs of the first and second shift registers, the first inputs of the first, second and third elements And are the third input of the transmitter, the outputs of the first shift register are connected to the second inputs of the first and second elements And, the output of the second register with The motor is connected to the second input of the third element AND, the output of which is connected to the first input of the trigger, as well as through the delay element to the first inputs of the fourth and fifth elements AND, the output of the first element AND is connected to the first element OR and the second input of the trigger, direct and inverse the outlets 5) of which are connected respectively, with the second inputs of the fifth and fourth elements And, the output of the second element And connected to the second input of the element OR, the third input of which is connected to the output of the fifth element And, the outputs of the element OR and the fourth element And connected respectively with the beginning and end of the primary winding of the output transformer The midpoint of which is connected to the power supply and the secondary winding is connected to the output of the transmitter. . 1 Jllr-l1 " " FIG. 2  LTUTJ JXrunnJTTLru-LrtrtrL- .... ll. one Editor K. Voloshchuk Compiled by N. Lazarev Tehred I. Popovich x . Order 2991/59 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries P3035, Moscow, Zh-35, Raushsk nab., 4/5 : Production and Printing Enterprise, Uzhgorod, Projecto st., 4 Proof. With. Shekmar