SU474051A1 - Device to enter information in the shift register - Google Patents

Description

Owls with an arbitrary arrangement relative to the clock, including those located in the interval between clock pulses, as well as rationing the pulse duration in the register.

This goal is achieved by the fact that the single output of the memory trigger is connected to the zero input of the feedback trigger, the zero output of which is connected to the zero input of the memory trigger and to the input of the first input key of the shift register, the matches of the second clock pulse and the output of the corresponding bit register shift register.

The device is performed on two static RS-type triggers: memory and feedback. The first of them remembers the impulse arriving at the information input. Information from the outputs of the memory trigger is entered into the register via shift register keys. The second trigger performs the functions of a negative feedback link: it is turned on only after the input of a pulse of the required duration into the register and, having turned on, stops entering information into the register. Both triggers are connected in such a way that after switching on the feedback trigger, the memory trigger and the feedback trigger are successively turned off and the circuit returns to its original state.

FIG. 1 is a diagram of the proposed device; in fig. 2 - time diagrams that show his work.

The device is made on elements AND AND NOT (OR OR NOT): element 1 constitutes an inverter, elements 2 and 3 a memory trigger, elements 4 and 5 a feedback trigger, element 6 a coincidence circuit. On lines 7 and 8, the first and second clock pulses are applied respectively. The device contains information input 9. The device outputs are connected via keys 10 to the inputs of a shift register with bits 11 and 12, having outputs 13-15. The output of one of the register bits is connected to the input 16 of the matching circuit 6.

The device works as follows.

The information pulse arrives at input 9 directly or through inverter 1 (with a positive pulse) to the single input of the memory trigger, i.e., the AND element. The trigger is activated regardless of the phase shift of the information pulse relative to the clock pulse. The only condition for triggering is:

INF - T

where D / T is the trigger on time. From the outputs of the memory trigger, the signals (logical "O and logical" 1) are sent to the input keys 10 of the shift register: to the first input key, "O - to the second. He blinked with the first clock pulse "1

is written to the first trigger of the first bit of the 11 shift register. The subsequent second clock pulse "1 is written to the second trigger of the first bit. The "1 for the first register bit" record continues until the register trigger operates, the unit output of which is connected to the input of the matching circuit 6. The matching circuit is triggered when it arrives

the inputs "1 from the corresponding register trigger and the second clock pulse" and generates a turn-on trigger signal for the reversing communication (the elements "AND - NOT 4 and 5) that are not available to its single input. Since the “1 from the single output of the memory trigger” acts on the zero input of the feedback trigger, “On on the single input of the feedback trigger it switches on this trigger. The signal from the zero output trigger feedback

enters the zero input of the memory trigger and the input key 10. The key is locked, the recording "1 in the register is terminated. If by this moment the pulse at the information input 9 of the device has ended, then

the memory trigger is turned off, and "O" from its single output goes to the zero input of the feedback trigger and turns it on after the second clock pulse ends. If by the time the trigger is activated

Since feedback has not completed the pulse at the information input, then before it ends, the single output of the memory trigger will be "1. At the end of the pulse at the information input, a memory trigger

under the action of "O at its zero input, it turns off and off the feedback trigger; the circuit returns to its original state. FIG. Figure 2 shows timing diagrams for cases where a pulse at the information input is located between clock pulses, and this pulse has a duration longer than the clock pulse following period (the numbers of the diagrams correspond to the numbers of elements and links in Fig. 1).

Timing diagrams correspond to the case where input 16 of the coincidence circuit 6 is connected to the unit output of the second trigger of the first register bit, i.e. output 14; while the duration of the pulses in the register

t „G.

To increase the pulse duration twice, threefold, etc., it is only necessary to switch the input of the coincidence circuit 6 to the output of the second trigger of the second, third, and so on bits of the register, respectively, while TC will be equal to 2T, 3T, etc.

Subject invention

A device for inputting information into a shift register containing a memory trigger, a single input of which is connected via an inverter to the information input of the device, a feedback trigger, whose single input is connected to the output of a circuit

coincident, the single and zero outputs of the memory trigger are connected to the inputs of the first and second input keys of the shift register, respectively, the inputs of both input keys are connected to the first clock pulse bus, characterized in that, in order to improve noise immunity and functional reliability, the single output of the memory trigger is connected to the zero input of the feedback trigger, the zero output of which is connected to the zero input of the memory trigger and the input of the first input key of the shift register, the input The coincidence circuits are connected to the second clock bus and to the output of the corresponding shift register register.

P P P P P P P

AND

ig. 2