SU424234A1 - SHIFT REGISTER - Google Patents

Description

one

The present invention relates to the field of computing.

Known shift registers on symmetric triggers and delay lines.

In a known register, a shift input is attached to each trigger. Applying a shear pulse causes all triggers to be reset and sending a reset pulse through the back delay to the next trigger.

The duration of the trigger pulse shift in a known register should not exceed the delay duration. The delay in such circuits, in order to ensure high speed, is chosen low, which imposes significant limitations on the duration of the trigger pulses. The second disadvantage is a large number of switchings, since all the triggers are reset first, and after some time - the delay time - the information is recorded in them. This leads to a decrease in the reliability and speed of the device.

The proposed device is free from these disadvantages. No tight tolerances are imposed on the duration of the shift pulses; moreover, the pulse duration can be infinitely long.

This is achieved due to the fact that the communication element between the bits is made in the form of an electronic pulse key, the control input of which is connected to the trigger output of the previous bit; the switching input is from the H1IIOI shift, which is connected via a delay line to the zero input of the first-stage trigger, and the key outputs connect the libi to the ipho, r: ma- terial inputs of the trigger of this bit.

Pa figs. 1 is a diagram of the proposed device; in fig. 2 - time diagram of the electronic key.

The shift register contains symmetric triggers 1, for example, transistor symmetric triggers, electronic pulse keys 2, in which a change in the control signal during the onset of the switching signal does not affect switching, and the delay line 3.

The proposed device works in the following way.

The inputs 4 in the symmetric trigger record information. The input to the shift input 5 of the shift pulse leads to the transfer of this pulse through the electronic keys 2 pa symmetric triggers n switching these triggers. The control of electronic keys is carried out from the previous trigger. The trigger of the first bit is reset to zero. A reset pulse through this trigger is fed through delay line 3, which is necessary in order to transmit via electronic keys before the trigger is switched.

Under the influence of a shift pulse, the triggers switch to new states and change the control signal on the electronic keys. However, switching changes do not occur, since it is not a common key that is applied, but a key in which at the moment the switching signal is supplied the control signal is memorized for the entire duration of the switching signal. The key has switching input 6, control input 7 and outputs 8 and 9. If there is no signal at input 7, the signal from input 6 is switched to output 9. If there is a signal at input 7, then the signal from input 6 is switched to output 8. Operation The key is shown in a timing diagram of FIG. 2, from which it is clear that the change in control

the signal at input 7 after the start of the signal on the input 6 does not affect the switching. The register is reset at input 10.

Subject invention

A shift register containing symmetric triggers and communication elements is distinguished by the fact that, in order to improve operation and reliability, the communication element between bits is made in the form of an electronic pulse key, the control input of which is connected to the output of the previous discharge trigger; switching input - with a shift,

which through the delay line is connected to the zero input of the trigger of the first bit, and the key outputs are connected to the information inputs of the trigger of the given bit.