SU488335A1 - Code Pulse Generator - Google Patents

Description

one

Diversion refers to impulse tech ike. The generator can be used in information transfer and radar systems to generate complex signals that modulate the daliomarne signal.

A known generator of code pulses, containing a / d-bit binary frequency divider, a n - 1 delay device, in parallel a key is connected in parallel to each other, and a majority logic element. In such a generator, delay devices are complex.

The purpose of the invention I | is to simplify the generator. For this, between the bits of the divider included devices delay "a

Lf

time mt /; .d, where f /, is the frequency at output 1 It

the previous bit, and the inputs of the major logic element are connected. To the outputs of the delay devices.

The drawing shows a block diagram of the proposed generator.

The generator contains bits 1-1 - 1-p binary frequency divider, devices 2-1 - 2- (p-1) delays, keys 3 and majority logic element 4. The output of the discharge l- (k-1) is connected through the included parallel device 2-k and key 3 to the -th input of element 4 connected to the input of the discharge - (). Exit bit 1-1

connected to the input port, element 4 input and the input of the discharge 1-2 directly.

The generator works as follows.

When a frequency 2 is applied to the generator input, 2 / there is a consecutive division in each frequency discharge frequency by 2 and a delay of frequency meanders 2/2-time. t 1 + where a ,, O or 1, respectively, with: deputy: whip or open key 3, and the delay time TL-i is equal to the sum delay of the meanders in devices 2-1 - 2- (k-2). At the output of element 4, a major logical function of n meanders is formed.

Claims (1)

Invention Formula A code pulse generator containing a bit double, an analog frequency divider n - 1 delay devices, in parallel to each of which a key is connected, and a majority logic element, different 25 by the fact that, for the sake of simplicity, the delay devices are switched on between the bits of the divider, j / r 1/4 /, where f / is the frequency at the output of the previous bit, and the inputs of the major clock logic element are connected 30 to the output delay device.