SU374747A1 - DEVICE FOR DIVIDING FREQUENCY FOLLOWING - Google Patents

Description

The invention relates to automation and computer technology, in particular to a frequency divider.

A device for dividing the pulse frequency, which consists of three elementary frequency dividers and co-ordination schemes, is known. However, in known devices, the division factors of the elementary frequency dividers must be mutually simple, which limits the possibility of obtaining large division factors.

The proposed device differs from the known fact that, in order to increase the frequency division factor, in it the outputs of the first and second elementary frequency dividers are connected to the inputs of the coincidence circuit, the output of the second elementary frequency divider is connected to the trigger input of the third elementary frequency divider, the output of which is connected to the fault input of the second elementary frequency divider, the fault input of the third elementary frequency divider is connected to the input bus and mplsov.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2- time diagrams of the device.

The frequency divider contains elementary frequency dividers (-7), a source of 8 pulses, and a coincidence circuit 9, 10, 11.

The output pulses from the source 8 pulses arrive at the inputs of the dividers 1-7. An output impulse from the coincidence circuit appears at the same time as the arrival of pulses from coincidence circuits 9 and 10. The frequency division factor at the outputs of these matching schemes depends on the division factors of the dividers / -6. FIG. 2 shows time diagrams of output voltages.

pulse source (f / s), dividers / and 2 frequencies (Ui and / 2) and coping scheme 9 (Ug for the case when the division factors of dividers 1 2 are three, i.e. ai G2 3, the factor a of divider 5 is equal to

unit.

Suppose that, at the initial moment in time, pulses appeared at the outputs of the divisors / and 2. Output impulse divider 2 starts divider 3. After one period of the input frequency

A pulse arrives at the fault input of the divider 5 from the pulse source 8, which resets the divider 3 to the initial zero state. The output pulse of divider 5 resets divider 2 to the zero state,

at the output of which a pulse appears again. The next pulse at the output of divider 2 appears after three periods of the input frequency (divider 3 is started again). way at the output of the divider

2, non-periodic pulse sequences appear. After a certain number of pulses of the input frequency, coincidence of i-pulses occurs at the inputs of the coincidence circuit 9. The frequency division factor at the output of circuit 9 coincides with K, - 9. If you select 3; 6 1, the frequency division factor at the output of the coincidence circuit 10 is also K, and 9. When a pulse appears at the output of the 10 ss circuit, the divider 7 is started and then the input frequency of the dividers and 5 is reset. At the output of the coincidence circuit 10 non-periodic pulse sequences appear. The total division factor at the output of the circuit 11 is equal to / (ii / C9 / Cio 81. Triggers can be used as dividers with a division factor equal to one. There are two requirements for the divider 3, 6 and 7: The name of the differentiating chain connected to the triggering input is chosen longer than the differentiating chain constant at the fault input; the output pulses of dividers 2, 4 and 5, but which are at the moment of their reset, should not change the states of dividers 5, 5 and 7. Subject of the invention. Device for The frequency of the pulse sequence, consisting of three elementary frequency dividers and coincidence circuits, characterized in that, in order to increase the frequency division factor, there the outputs of the first and second elementary frequency dividers are connected to the inputs of the coincidence circuit, the output of the second elementary frequency divider is connected to the trigger input of the third elementary frequency divider, the output of which is connected with the reset input of the second elementary frequency divider, the reset input of the third elementary frequency divider from It is uniform with the bus of input pulses.

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