SU1695518A1 - Device for protection against impulse noise - Google Patents

Abstract

The invention relates to radio engineering and can be used in receiving equipment for various purposes. The purpose of the invention is to increase the noise immunity from impulse noise, which is a mixture of radio pulses and single radio pulses. The device for protection against impulse noise contains a delay element 1, an interrupter 2, a limiting amplifier 3, a pulse detector 4, a shaper 5, the first RS flip-flop 6, the first element OR 7, the first counter 8, the first element And 9, the second element And 10 , the second element OR 11, the second counter 12 and the second trigger 13. By introducing the first RS trigger 6, the first element OR 7, the first counter 8, the first element AND 9, the second element AND 10, the second element OR 11, the second counter 12 and the second trigger 13 is provided with an overlapping pulse blocking in the whole burst of interference noise type signal of the Loran system. 2 Il.

Description

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The invention relates to radio engineering and can be used in receiving equipment for various purposes.

The purpose of the invention is to increase the noise immunity from impulse noise, which is a mixture of radio pulses and single radio pulses.

FIG. Figure 1 shows the structural electrical circuit of the impulse noise protection device; in fig. 2 -pipes of stresses.

The device for protection against impulse noise contains a delay element 1, an interrupter 2, a limiting amplifier 3, a pulse detector 4, a driver 5

level, the first RS-flip-flop 6, the first element OR 7, the first counter 8, the first element And 9, the second element And 10, the second element OR 11, the second counter 12 and the second RS-trigger 13.

The device works as follows.

The delay element 1 provides a delay in the input to the device of the mixture of the useful signal and interference for the time of the formation of the control signal arriving at the second input of the chopper 2.

The mixture of the desired signal and interference through the limiting amplifier 3 is also fed to the pulse detector 4, which highlights the pulse interference envelope. At a certain amplitude of this envelope, the shaper 5 is triggered and the RS flip-flop b is set to the Control signal state and the first counter 8 is set to the initial state. to the second input of the chopper 2. The chopper 2 opens the signal path and the impulse noise does not pass, therefore, to the output of the device. The signal from the second (inverse) output of the first RS flip-flop b is fed to the second counter 12 and through the first element OR 7 to the first counter 8, enabling the operation of these nodes. The initial state of the second RS flip-flop 13 corresponds to the prohibition of the signal passing through the second element AND 10 and allowing passage through the first element 9, which corresponds to the appearance of a reset signal at the output of the second element OR 11 at time ti.

If the next interference pulse is detected in time Ti ti (Fig. 2a), the reset pulse returns the first RS flip-flop to the initial state, therefore, the control signal from the output of the first RS flip-flop b will end, which opens the interrupter 2 ( will close the signal path), and,

in addition, it will return the second RS-trigger 13 to the initial state and disable the operation of the first counter 8.

If the next interference pulse is detected in time Ta ti, it will set the first counter 8 to the initial state, and the state of the first trigger 6 will not change (since it is already in the Control signal state). The counting time by the first counter 8 starts again, which increases the duration of the control signal (this duration should be no longer ti, but T2 + ti).

If the third impulse interference on Wits

5 through time Tz ti after the second one, then the first counter 8 again returns to the initial state before the control signal (the duration of which should now be T2 + T3 + ti) ends. Thus, a control signal is generated that overlaps the burst of interference pulses.

If a burst of interference pulses has arrived and the control signal exceeds some predetermined time tyi over time, then the second RS trigger triggers 13 overturns through time tyi, the first element And 9 will be banned, and the second element And 10 will be reset and reset pulses The first RS flip-flop 6 is sent through time t2 (Fig. 2c). After the termination of the control signal, the second RS flip-flop 13 returns to its original position and the device is ready to repeat the described operations.

5 The intervals ti and t2 are created by recalculating the pulses of the reference frequency f3r.i by the first counter 8, the outputs of which are connected to the inputs of the elements 9 and 10. The interval tyi is created by recalculating

0 pulses of the reference frequency f3T2 second counter 12, the output of which is connected to the setup input of the second RS-flip-flop 13.

The signal from the output elements And 9 and 10

5 (the second RS flip-flop 13 opens at each moment only one of these circuits) through the second element IL AND 11 enters the reset input of the first RS flip-flop b. After resetting the first RS flip-flop 6, the strobe stops

0 is applied to the breaker, as well as through the first element OR 7, a reset signal is sent to the first counter 8, which is reset to 0 and remains in this state. Through the first element OR 7, the first counter 8 is reset to O by the pulse coming from the level 5 generator (but after the end of the pulse this reset signal stops).

When the signal is reset from the first RS-flip-flop 6, the second RS-flip-flop 13 enters the initial state, at which the first element AND 9 is enabled. At the second exit of the second RS-flip-flop 13, connected to the input of the second element I 10, at this time there is a signal O, which prohibits the operation of the second element I 10 (more precisely, it prohibits the passage of a signal through it). When the Reset signal ends (which occurs after the first RS flip-flop 6 is flushed by a signal from the level generator), then through tyta 4 Theta 4 ms, the second RS flip-flop 13 and 1 will be tipped back to the input of the second element I 10, allowing it to work (with In this case, the first element AND 9 is closed, since the signal O) is set at the inverse output of the second RS flip-flop 13.

The first RS flip-flop 6, the first element OR 7, the first counter 8, the first 9 and the second 10 elements AND, the second element OR 11, the second counter 12 and the second RS flip-flop 13 constitute the control signal duration generator to the interrupter 2. This The duration driver provides the blocking pulse of the entire burst of interference signals such as the Loran system signal.

Claims (1)

Claims An impulse noise protection device comprising a series-connected delay element and an interrupter, an amplifier-limiter connected in series, the input of which is connected to the input of the delay element and is the device input, a pulse detector and a level driver, characterized in that in order to increase the noise immunity from impulse noise, which is a mixture of radio pulses and single radio pulses, the first RS trigger, the input of the preliminary installation and the direct output of which are connected respectively to the output of the shaper and the interrupter control input, are introduced, the first element OR first and second the input of which is connected respectively to the output of the level generator and to the inverse output of the first RS flip-flop, the first counter, the reset input of which is connected to the output of the first OR element, the first AND element connected in series, the first and second inputs of which are connected respectively to the outputs of the 1st and th, where ik, bits of the first counter, and the second element OR, the output of which is connected to the reset input of the first RS flip-flop, the second element AND, the first, second inputs and output of which are connected respectively to the outputs of the 1st (K + 1) th bit to first counter and the other input of the second OR gate, a second counter, whose reset input is connected to the inverted output of the first RS-flip-flop, a second RS-trigger, m presetter whose input is the reset input connected respectively to yield The second counter and the inverse output of the first trigger, the inverse and direct outputs of the second RS trigger are connected respectively to the third input of the first element And to the third input of the second element And, the counting inputs of the first and second counter are respectively the inputs of the first and second reference frequency. I I I I I I And FIG. 2 interference interference