SU1095427A1 - Device for protecting against pulse noise - Google Patents

Abstract

A DEVICE FOR THE RESERVED PULSE FRAMEWORK, containing a binary counter, the output of one of the bits of which is connected to the first input of the first match element, the output of which is the device output, and the inverse output of the counting trigger connected to the first input of the second coincidence element, characterized in that in order to increase noise immunity by suppressing multiple pulse interference, three additional coincidence elements and an inverter are inserted into it, the inverter input being combined with the first input of the first additional of the complete matching element whose output is connected to the input of the binary counter and the second input of the first matching element via the second additional matching element, to the other input of which the output of the second matching element is connected, to the other inputs of which the inverter output and the output of the third additional coincidence element, to the inputs of which the inverted output of the counting trigger is connected, the output of the corresponding bit of the binary counter, and a clock input of a binary counter, the other bits of which are connected to the corresponding inputs of the first match element whose clock input is combined with a clock input of a binary counter, and the output of the first match element is connected to the corresponding input of the second additional element of the coincident trigger input the input of which is connected to the output of the third additional element of coincidence, and the direct output of the counting trigger is connected to the second input of the first additional elec cient match.

Description

The invention relates to radio engineering and can be used in receiving devices of information exchange systems subject to the effects of impulse noise.

A device for protection against impulse noise is known, containing the first matching element connected in series, the first input of which is connected to the device input, and the trigger output connected to the second input, the output of the delay element is connected to the counting inlet of the second matching element, the output of the first matching element is connected 15 to the second input of the second match element and to the input of the delay element executed in the form of a counter on two triggers, and to the additional input of the first match element There is a clock, and the input inputs of the device, the output of which is the output of the second coincidence element, is connected to the setup inputs of the trigger element of the delay element. However, the known device does not provide noise suppression of the type of Loss of impulse and has a low noise immunity. The device for protection against impulse noise contains a binary counter, the output of one of the bits of which is connected to the first input of the first match element, the output of which is the output of the device, and the inverse output of the counting trigger , the output of the first element of the match is connected to the input of the counting trigger, the reset input of which is combined with the second inputs of the first and second elements of the match and with the setting inputs of the trigger elements This delay is connected to the output of an OR element, whose inputs are combined through a delay 2 block. The disadvantage of this device is low noise immunity due to repeated impulse noise. The purpose of the invention is to increase the noise immunity by suppressing multiple impulse noise. This goal is achieved in that a device for protection against impulse noise contains a binary counter, the output of one of the bits of which is connected to the first input of the first coincidence element, the output of which is the output of the device, and the inverse output of the counting flip-flop is connected to the first input of the second match element, three additional match elements and an inverter are introduced, and the inverter input is combined with the first input of the first additional match element, the output of which is connected to the input. a binary counter and to the second input of the first matching element through the second optional matching element, to the other input of which the output of the second matching element is connected, to the other inputs of which the inverter output and the output of the third additional matching element are connected, to the inputs of which the inverse output h is connected: the trigger, respectively, the output of the corresponding bit of the binary counter and the clock input of the binary counter, the other bits of which are connected to the corresponding input of the first match element, the clock input of which is combined with the clock input of the binary counter, and the output of the first match element is connected to the corresponding input of the second additional match element and to the input Setting O of the counting trigger, the output of the third additional match element is connected to the clock input, and the output of the counting trigger is connected to the second input of the first additional match element,. The drawing shows an electrical diagram of the proposed device. A device for protection against impulse noise, contains a binary counter 1, a counting trigger 2, the first and second elements of coincidence 3 and 4, the first, second and third additional elements of coincidence 5-7 and the inverter 8. The device for protection against impulse noise operates as follows . The device with a low potential at the control input and the sync pulses received by the clock clock of the VCOA is set to the initial state, in which the binary counter 1 is reset and the counting trigger 2 is in the unit state, i.e. all the outputs of the counter and the inverse output of the counting trigger 2 have a low potential, and the forward output of the counting trigger 2 has a high potential, while the outputs of the first and second elements 3 and 4 and the first and third additional elements 5 and 7 have a low potential potential, and at the output of the second additional element 6 coincidence there is a low potential. When a high pesticiald appears on the control input, a low potential appears at the output of the first additional coincidence element 5, causing the appearance of the second additional high potential coincidence element 6 at the output, which allows the input of a clock pulse to the binary counter 1. Thereby control over the duration of the incoming pulse to the control input. If the pulse ends. Before the binary counter 1 is filled and a gating clock appears at the clock input of the synchronization pulse, then an interference pulse is applied to the control input. In this case, binary counter 1 is zeroed out, and at the output of the first element 3 a match, and therefore at the output of the device, a signal does not appear. Those. False pulse type interference is suppressed by the device. The described process is repeated every time after the appearance of a false pulse, which indicates that the device suppresses a false interference of the false pulse type. The presence of a pulse at the installation input of binary counter 1 at the time of the appearance of a gating pulse, which occurs after the filling of binary counter 1, indicates that an information signal is present at the control input. Therefore, the gate clock pulse is inverted at the output of the first element 3 of the match and is fed to the output of the device. At the same time, the low potential from the output of the first element 3 coincides with the counting trigger 2. The potential set at the inverse output of the counting trigger 2 is high, allowing the signal at the output of the third additional element to coincide further, while co-ordinating in time the presence of a certain code in binary counter 1 and clock at the clock input. The low potential, set at the direct output of the counting trigger 2, sets the 10 7 high potential at the output of the first additional element 5 to coincide. A high potential is present at the output of the second coincidence element 4, the trigger connections between the first coincidence element 3 and the second additional coincidence element 6 are due to the fact that the signal at the device output is exactly equal in duration to the gating clock pulse, regardless of the potentials acting on the inputs of the second element 4 match and the first additional item 5 match. With the trailing edge of the gating clock pulse, binary counter 1 overflows and a low potential is established at all its outputs. At the same time, a low potential is set at the output of the second additional element 6, which prohibits the input of clock pulses to binary counter 1, if a high potential is still present at the control input. If a low potential appears at the control input during the formation of a pulse at the output, this will not affect the duration of the output pulse. After the end of the output pulse, if there is a low potential at the control input, the output of the second additional element 6 is still there is a high potential, keeping low potential from the output of the second element 4 coincidence. The control process begins according to the duration of the pause between pulses. Binary counter 1 from zero state counts sync pulses. If the pause between pulse 1 W at the control input is finished before the binary counter 1 is fixed, a certain code combination is detected and a clock pulse occurs, i.e. the third additional element 7 is switched, this indicates that the disturbance and binary counter 1 are zeroed at the control input. This does not affect the output of the device. Formally, the Impact of Ipulse type interference does not occur at the output of the device. When a pause occurs between the pulses at the control input, binary counter 1 monitors its duration and is reset to the zero state if it is determined that there is interference on the control input. In this way, the device suppresses the type of multiple interference of the type Impulse Drop. If the pause between pulses has a sufficient duration so that a certain code combination is fixed in binary counter 1, after which a sync pulse arrives at the input of the third additional matching element 7, this means that there is a pause between information signals at the input control. Therefore, the third additional match element 7 is switched. A high potential is established from its output at the outputs of the second element 4 of the match and the first additional element 5 of the match, which results in the output of the second additional element 6 of the low potential tangling the binary counter 1. Resetting the binary counter 1 causes the appearance of high potential at the output of the third additional element 7 coincidence. The counting trigger 2 is switched to a single state and the device returns to its original state. Thus, when an information pulse arrives at the control input of the device, a pulse is formed at the output of the device that coincides in duration and phase with the sync pulse acting on the clock input of the device. Moreover, multiple impulses of interference of the type False impulse, Loss of impulse do not cause false triggering of the device, i.e. suppressed by the device. In the proposed device, multiple interference, such as a false pulse and the loss of a pulse does not pass to the output, i.e. multiple interference is suppressed by the proposed device. This is because in the proposed device the duration is monitored independently whether the signal at the control input is a false pulse or information signal. Only after determining that the signal at the control input is informational, is the output pulse gating by the sync pulse, i.e. the output pulse coincides in duration and phase with the sync pulse, after which the device switches to the control mode in duration, regardless of whether the signal at the control input is a pause between information signals or disturbance of the type Pulse Failure. In this mode, regardless of the results of the control, the appearance of the signal at the device output is excluded. After determining that the signal at the control input is a pause between information signals, the device returns to the monitoring mode independently whether the signal at the control input is an information signal or a False pulse type noise. Moreover, the proposed device provides for the suppression of any number of consecutive interferences of the same type, since the device returns to the initial state each time if, as a result of monitoring by duration, it is determined that the signal at the control input is an interference. In the known prototype device, multiple interferences of the type False impulse and Loss of impulse are transmitted to the output of the device. This is due to the fact that the delay unit does not suppress the interference, but only shifts it in time. Therefore, an element from the output of a delay unit can arrive at the first input OR interference at a time when a similar interference from the control input of the device is present at the second input of the OR element. The coincidence of interference at the inputs of the element OR leads to the passage of interference at the output of the element OR. If in the considered case the elements of the OR pulse are present at the inputs of the False impulse type, they are summed at the output of the OR element, which, with the corresponding duration of the total interference at the output of the OR element, causes the binary counter to be filled with sync pulses and a false signal at the device output. Those. already two interferences of the False impulse type cause false triggering of the device. If the elements of the pulse overlap type act on the inputs of the OR element, then the output of the OR element causes interference, immediately resetting the binary counter and the counting trigger to the zero state, which causes the binary counter to repopulate and form a second output pulse, which is ozhny. Those. already two type interference

The loss of a pulse causes a false alarm of the known device. With a greater number of consecutive noise of the same type acting on the control input, the number of false positives of the known device

increases accordingly. Thus, the known device does not provide suppression of multiple impulse noise, .e. has low noise immunity relative to the proposed device.

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Claims (1)

DEVICE FOR MOUNTING PROTECTION AGAINST PULSE INTERFERENCE, containing a binary counter, the output of one of the bits of which is connected to the first input of the first coincidence element, the output of which is the output of the device, and the inverse output of the counting trigger is connected to the first input of the second coincidence element, characterized in that, for the purpose of increasing noise immunity by suppressing repeated pulsed noise, three additional matching elements and an inverter are introduced into it, while the inverter input is combined with the first input of the first additional a coincidence element, the output of which is connected to the setting 0 of the binary counter and the second input of the first coincidence element through the second additional coincidence element, to the other input of which the output of the second coincidence element is connected, to the other inputs of which the inverter output and the output of the third additional element are connected coincidence, to the inputs of which are connected respectively the inverse output of the counting trigger, the output of the corresponding bit of the binary counter and the clock input of the binary counter ka, other bits are connected to respective inputs of the first matching element; the clock input of which is combined with the clock input of the binary counter, and the output of the first match element is connected to the corresponding input of the second additional match element and to the input Setting 0 of the counting trigger, the output of the third additional match element is connected to the clock input, and the direct output of the counting trigger is connected to the second the input of the first additional matching element. >