SU1686432A1 - Device for information input-output - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter and transmit information to various devices and systems. The purpose of the invention is to expand the field of application of the device and increase the speed of data transmission to an external device (WU) due to the organization of additional input and output information modes. The device for input-output information contains a keyboard 1, an encoder 2, a group of counters 3, a second decoder 4, a second indicator 5, the first element OR 6, a distributor 7 pulses, a third element OR 8, the first decoder 9, the first indicator 10, the second element OR 11. control unit 12, fourth element OR 13, group of registers 14, element OR NOT 15, sixth element AND 16. ninth element OR 17, memory block 18

Description

The invention relates to automation and computing and can be used to enter and transmit information to various devices and systems.

The purpose of the invention is to expand the field of application of the device and increase the speed of data transmission to an external device due to the organization of additional modes of input and output information.

Fig, 1 shows a functional diagram of the device; in fig. 2 shows a pulse shaper driver; in fig. 3 and 4 - timing charts of the device.

The device for input-output information contains a keyboard 1, an encoder 2, a group of counters 3, a second decoder 4, a second indicator 5, the first element OR 6, a distributor 7 pulses, a third element OR 8, the first decoder 9. the first indicator 10, the second element OR 11, control unit 12, fourth element OR 13, group of registers 14, element OR NOT 15, sixth element AND 16, ninth element OR 17, memory block 18, first trigger 19, second element AND 20, second trigger 21, the fifth element And 22, shaper 23 pulses, the eighth element OR 24, shaper 25 pulses sequences, counter 26. fifth element OR 27, seventh element OR 28, third trigger 29, tenth element OR 30, sixth element OR 31, fifth trigger 32, eleventh element OR 33, sixth trigger 34, third element AND 35 pulse generator 36, fourth trigger 37, third indicator 38, fourth element AND 39, seventh trigger 40, inputs and outputs 41-46 of driver 25, first element And 47,

The shaper 25 pulse sequences contain the element OR 48, the generator 49 of pulses, the element NOT 50, the trigger 51. the element AND 52, the trigger 53 and the element And 54.

3 group counters are designed to record the parcel number. The number of these counters is determined by the number of parcels.

which are recorded and stored in memory block 18. So, for example, if the number of parcels used is determined by a three-digit number, then the number of counters is 3

 3 ().

The number of registers of a group of 14 is determined by the number of characters m in each parcel.

The distributor 7 pulses can

be the same as in the known device.

The memory unit 18 may be of semiconductor type (static RAM). The memory block includes N 1-bit cells.

memory The number N is determined by the maximum number of information packets to be recorded and stored in the memory block. The number I is determined by the size of the code send. Code

the state of the counters 3 determines the address A1 of the memory location in which the package is written. Counter 26 has I states and determines the address of the bits of the memory cell.

The first 10 and second 5 indicators

are sign-synthesizing indicators, for example, semiconductor type. The third indicator 38 includes two LEDs (or can also be made in the form of symbolic indicators).

Triggers 19, 21, 32, 34, and 37 are D-flip-flops. Inputs D of these triggers are connected to the device power bus (not shown). Trigger 40 is a T-flip-flop.

The device provides input, indication (for the purpose of checking the correctness of the input), writing to the device’s memory block and storing a group of different in structure

information packages; reading at the request of the operator and indication of information packages stored in the memory block, without transferring them to an external device; sequential, one-time or multiple, automatic (without operator) transmission to the external device of all or part of the memory stored in the memory unit

devices of information parcels with a specified time interval between shipments; sequential, with the participation of the operator, a single or multiple transfer to the external device of all or part of the information packages stored in the memory block of the device with arbitrary time intervals between the packages determined by the operator; a one-time or multiple transmission to an external device at an arbitrary point in time of any of the information packages stored in the memory of the device; operative change of the content of any of the information packages stored in the memory block; receiving information counts from an external device, displaying them, writing to a memory unit for storage and subsequent repeated reading and display at the request of the operator; arbitrary combination at the request of the operator specified modes.

The device works as follows.

When a voltage source is supplied to the voltage source device, a short pulse is generated at the output of the pulse shaper 23, which through the OR element 27 enters the installation inputs of the counter 26. Triggers 19, 32, 34, 37, 51 and 53, through the OR element 31 to the installation input of the trigger 40, through the IL-24 element to the installation input of the trigger 21 and through the OR element 28 to the installation input of the trigger 29 and sets them to the initial zero state. Since O is present at the output of the flip-flop 40, the pulse generator 36 does not work and the flip-flop 37 continues to be in the zero state. Since the triggers are 19. 29,

32,34 and 37 are in the zero state, then at all four inputs and output of the element OR 30, as well as at the output of the element OR

33, at the inputs 41 and 42 of the generator 25 of the pulse sequences is O. In this case, the output of the IL-48 element (Fig. 2) is O, and the pulse generator 49 does not work. At outputs 44 and 46 of the pulse sequence generator, O is located, and at its output 45 and, respectively, the synchronization input CS of memory block 18 is 1. At the 3 / C (write-read) gate of memory 18, logical O is present and the specified block is in data reading mode. However, data reading does not occur, since there are no CS sync signals (active low levels) and the output of memory block 18 is O. Since O is at the output of the OR 33, then the Strobe outputs are available.

Package and Sync. device also present o.

Input, indication, and writing to the memory of the device of the group of information packages is carried out as follows.

Before entering the information device into the device, the operator presses the Enter service button and a logical 1 signal appears at the input of the input, which is applied to the automatic input of control unit 12, and a logical signal 1 appears at the second output of control unit 12 - inputs of registers of the 14th group, preparing them for the parallel data entry mode. Clock pulses from the first output of the control unit 12 pass through the element OR 6 and enter the counting input of the distributor 7 pulses, which leads to multiple

0 its run and the sequential appearance at its outputs of signals that implement the recording of gate inputs to counters 3 and registers 14 of information supplied to their inputs of parallel input. So

5, as these inputs are received at this time with zero information from the output of the encoder 2 (none of the character keys are pressed yet), then counters 3 and registers 14 will be repeatedly recorded O. This leads to reliable resetting of counters 3 and registers 14, which checked by indications of indicators 5 and 10.

After releasing the Enter button, the corresponding signal disappears, and a short pulse appears at the third output of control unit 12, which flows through the OR 8 element to the distributor 7 of the pulse and resets it to O. The device is now ready for a parallel WALK into it information.

0 Then the operator successively presses the keys of the keyboard 1. enter the required information: the number of the first parcel and the parcel code. After the first press of one of the keys, the signal from her contact goes to

5 encoder 2 and converted into a parallel binary code of this character, which is fed to the inputs D of parallel recording of counters 3 and information inputs of D2 registers 14. As a result of pressing the keyboard, the code sign signal (logical 1) from the output of the encoder 2 enters through the OR 6 element the counting input of the distributor 7 pulses and at its first output a signal appears that is fed to

5, the gate input of the first counter 3 of the group, which records the information of the encoder 2. The contents of the first counter 3 through the decoder 4 are displayed on the indicator 5 in order to monitor the correctness of the input. After pressing the next key of the keyboard 1, the signal appears at the second output of the distributor 7 pulses and the code of the pressed key is recorded in the second counter of group 3. As a result of (n + 1) -th pressing one of the keys, the corresponding code will be written into the first register of the 14th group, etc. After (n + m) -ro pressing, all data corresponding to the first information parcel will be entered. At the same time, in the counter 3 The parcel number will be recorded, and the parcel code will be written to group registers 14. Each character entered is weighted in the corresponding digit of indicators 5 and 10.

The operator then checks the correctness of the input on indicators 5 and 10. In case of errors, the operator presses the Enter button (as described above, counters 3 and registers 14 are reset to the zero state), and then re-enters the required information.

Having checked the correctness of the data input, the operator must record the entered information in the device’s memory block, for which he presses the Record button. At the same time, the same signal is generated, which arrives at control unit 12, at the first input of the OR element 8 and at the trigger input of the trigger 19. The rising edge of the signal The recording causes the switch of the distributor 7 pulses to the zero state through the OR 8 element. This is necessary so that the (n + ch) th output signal does not interfere with the operation of registers 14- groups. In addition, under the action of the Write signal, a logical O signal appears at the second output of the control unit 12, which switches the group register 14 to the sequential shift mode. At the same time, the Recording signal triggers the trigger 19. From this point in time, the information entered into registers 14 is recorded in the cell of memory 18, whose address is determined by the state of counters 3, i.e. the number of the parcel. Timing diagrams explaining the operation of the device in the Record mode are shown in FIG. 3.

At the output of the trigger 19, 1 appears (Fig. 3a), which is fed to the input 3 / C of the memory block 18, to the elements AND 20, 47, to the output 41 of the generator of 25 pulse sequences and, accordingly, through the element OR 48 to the input of the generator 49 pulses (Fig. 2). When this happens the following: the memory block 18 is transferred to the data recording mode: the AND 20 element allows the passage of signals from the last bit of the last register 14 of the group to the input of the OR element 11 and then to the D1 input of the first register of the group 14, AND 47

permits the passage of a pulse sequence formed at the output 44 of the generator of 25 pulse sequences to the first input of the element OR

13, the pulse generator 49 starts its operation and generates pulses (FIG. 36). At the output of the element NO 50, pulses are formed (FIG. Sv), inverted with respect to the pulses generated

0 by the generator 49. In this case, the trigger 51 operates in the division mode by 2 (Fig. 3g, d) and is triggered by the leading edge of the pulses arriving at its clock input. The trigger 53 is triggered by the first positive signal differential occurring at its clock input (Fig. Ze) and is in state 1 until signal 1 is received at its setup input. Pulses at the inverse output

0, the flip-flop 51 (Fig. A) is the synchronizing pulses input to the CS of the memory unit 18. The pulses generated at the output of the element And 52 (Fig. ЗЖ), shift the information into the register of 5 pax 14 groups and change the state of the counter 26. Since none of the triggers 29, 32, 34 and 37 are in 1, then the output of the element OR 30, at the input 42 of the imager 25 pulse sequences and

0, respectively, at the input of the element And 54 is present O. In this case, the element And 54 prohibits the formation of an impulse sequence at its output and there is an O at it. At the inputs of the C1 registers 14

5 through the element AND 47 and OR 13 only the impulses generated by the element And 52 arrive.

In the time interval ti-t2 (Fig. 3), the information input of the memory block 18 is at the logic level (Fig. Zi), determined by the last bit of the last register of group 14 (the first bit of the packet). Recording this information for the first time in the cell of the memory block 18, whose address is

5 is determined by the zero state of the counter 26, carried out by the zero signal level CS (Fig. A).

At time g, an output appears at the output 44 of the pulse sequence maker, which is transmitted through the AND 47 and OR 13 elements to the clock inputs C1 of the group 14 registers, and the contents of the registers are shifted by one bit to

5 output (in the direction of the last bit of the last register associated with the information input of the memory block 18). At the same time, the counter 26 increases its state by one and generates the address of the second bit of the first memory cell of the memory block 18. Then, the zero-level pulse, acting on its input CS, records the second bit of the send to the second bit of the first cell of the memory block 18. In the same way, the remaining bits of the send are written into the memory cell.

During the whole Recording cycle, counters 3 do not change their state, since the signals at their gating and counting inputs are not formed. The signals on the gate inputs do not form because the keyboard 1 keys are not pressed and the pulse distributor 7 does not work, and the counting counters' pulses are not generated, because the Per. O button is not pressed, and the pulse generator 36 does not work.

Since, in the Record mode, the AND 20 element allows the passage of signals from the output of the last 1st bit of registers 14 to the second input of the OR 11 element, simultaneously with the recording of the information package in the memory block 18, it is overwritten in the group registers 14.

At time t, 3, when the 1st pulse appears at the output 44 of the pulse sequence generator, a short pulse appears at the transfer output of counter 26, which through the OR 27 element r arrives at the installation inputs of the flip-flops 19 , 51 and 53 and sets them to the initial state (Fig. 3). At this point in time, the recording of the first information packet to the first cell of the memory block 18 is completed. FIG. Ze is given as an example one of the possible code combinations of the information parcel. After the end of the recording, the parcels to the memory block 18 in the counters 3 and the registers 14 will again be found, and on the indicators 5 and 10 the data previously entered by the operator will be displayed. In this case, the operator can verify the correct functioning of the device in the Record mode.

To enter and write to the memory block of the second information package, the operator presses the Enter button again, then uses the keyboard to enter the second number of the information package (this changes the address of the cell of memory block 18) and the contents of this package, and then presses the Record button . In this case, the second parcel is recorded in the second memory location. Similarly, all other parcels are recorded in memory block 18. Information parcels are stored until the power supply voltage of the device is removed or the data of the parcels is not replaced by others.

It should be noted that in the process of writing the information parcels to the memory block, the strobe signal at the output of the OR 33 element is absent; as a result, the And 35 and 39 elements do not pass the signals to the Sending and Sync outputs. (synchronization) of the device, i.e. there are no signals on all outputs of the device.

The reading of the data stored in the memory unit 18 and its indication are carried out as follows.

As a result, press the Read button. (reading) the signal of the same name arrives at the trigger input of the trigger 21 and translates

it in a single state. At the same time, the corresponding LED on the indicator 38 lights up, indicating that the device is in the data reading mode. Signal logic 1 output

trigger 21 is fed to the input of the element And 22 and allows the passage of the output pulses to the second input, as well as the information input of the trigger 29, preparing it to trigger. Data reading from memory block 18 can be performed immediately after they are written to verify the correctness of the record. In this case, the registers 14 continue to remain in the data shift mode, and the pulse distributor 7 is in the initial zero state.

The operator then enters the parcel number, the contents of which must be read.

from block 18 of memory. After the first keystroke key 1, the code of this character is recorded in the manner described above in the first counter 3, after the second keystroke in the second, and so on. After the nth keystroke

The last digit of the parcel number will be recorded in the last counter of the 3rd group by a signal appearing at the n-th output of the distributor 7 pulses. The entered parcel number is displayed on the indicator 5.

The parcel number recorded in counter 3 determines the cell address of the memory unit 18 in which the parcel is stored. At the same time, the signal formed at the nth output of the distributor 7 pulses is fed to the clock input of the trigger 29 and translates it into a single state. The logical signal 1 from the output of the trigger 29 through the emand OR 30 is fed to the input 42 of the pulse shaper sequence.

From this point in time, the parcel stored in memory block 18, the number of which is entered into the counters 3, is read and written to the registers 14. Time diagrams explaining the operation of the device in this mode are shown in FIG. four.

The signal logic 1 from the output of the trigger 29 (Fig. 4A) through the element OR 48 is supplied to the generator 49 pulses and. in addition, the input element And 54 enters. At the same time, the pulse generator 49 (Fig. 46), the NO element 50 (Fig. 4c), the trigger 51 (Fig. 4d, d), the trigger 53 (Fig. 4e) start to work. At the outputs 45, 44 and 46 of the mapper 25, pulse sequences appear, which are fed respectively to the input CS of the memory unit 18 (Fig. 4e), which is in data reading mode, to the input of the And element 47 and to the counting input of the counter 26 ( Fig. 4L) and the third input of the element OR 13 (Fig. 4g). Since the trigger 19 is in the zero state, the element AND 47 does not allow the pulses generated at the output 44 of the driver 25 to be passed to the input of the element OR 13, and O is present at its output. Consequently, only the pulses generated by the output 46 of the driver 25. For the same reason, the element AND 20 does not allow the input of the element OR 11 signals appearing in the last bit of the last register 14 of the group, and its output contains a logical O.

8, the time interval ti-t3 is read by the low-level signal CS and occurs at the output of memory block 18 of the first discharge bit (for example, logical 1 in FIG. 4i). The first pulse appearing at time t2 at the output 46 of the driver 25, the signal appearing at the output of the memory block 18, is recorded at the input D1 in the first digit of the first register 14 of the group (Fig. 4k). At time point to, the counter 26 under the action of the pulse generated at the output 44 of the driver 25 (FIG. 4L) increases its state by one and forms the address of the second bit of the memory cell where the second bit of the parcel is stored. In the time interval tj-t4, a second bit (logical O) appears at the output of memory block 18, which is then written to the first bit of the first register 14, the previous contents of which will be shifted to the second bit, etc. In a similar way It reads from the memory block 18 all the remaining bits of the package.

At time ts. when the output 44 of the driver 25 on Wits 1st pulse. at the transfer output of the counter 26, in Vits, a short pulse (Fig. 4m), under the action of which the triggers 51 and 53 and the counter 26 transitions to the initial zero state. At the same time this signal through the elements OR 27, the element AND 22 and the element OR 28 is fed to the installation input of the trigger 29

and brings it to the initial zero state (Fig. 4a). In this case, the operation of the driver of 25 pulse sequences is terminated. In addition, the impulse from the output

transfer of the counter 26 through the element And 22, and then through the element OR 8 enters the input of the installation of the distributor 7 pulses and resets it to the zero state. Thus, from time ts to

0 counters 3 and registers 14 will contain the parcel number and its code, respectively. This information is transmitted through decoders 4 and 9 to indicators 5 and 10 for visual perception. Trigger 21 when

5 this continues to be in a single state.

Similarly, the operator can read from the memory block 18 and display other parcels. In this case, the parcel readout time can be arbitrary and is determined by the sequence of setting their numbers. So, to read any next parcel, the operator simply enter into the counters 3 its number. With

In this, with the input of the last digit of the number, trigger 29 is again triggered, and from memory block 18, the package stored in the memory cell whose address is determined by the number (number) entered in the counters 3 is read as described above. This package is displayed then on display 10.

In the data read mode, the triggers 32, 33 and 37 are in the zero state, the strobe signal at the output of the element

5 OR 33 is absent; therefore, elements 35 and 39 do not pass the signals to the outputs Parcel and Sync. devices, i.e., there are no signals on all outputs of the device and data transmission to the external

0 device does not occur.

The presence of the read mode allows the operator to perform a sequential or selective check of the contents of the cells of the memory block 18 before directly sending the packages to an external device.

Automatic transfer to the external device of all or part of the information packages stored on the memory block

0 is performed as follows.

If the data is transmitted immediately after they are written to the memory unit without being taken out of reading for the purpose of verification, the operator must first

5 put the device into read mode. pressing the Read button. If the device is already in read mode, the operator immediately enters into the counters 3 the number of the first parcel from which the sequence of the parcels stored in memory block 18 is output to the external device. After entering into the counters C of the last digit of the first parcel number, the code of this parcel is read from memory block 18 and written to registers 14. After that, the device continues to be in read mode. The parcel number and its contents are displayed on indicators 5 and 10, and the operator can be visually convinced that the original parcel has been set correctly. In this case, the output to the external device of the signals at the outputs of Strobe., Parcel and Sync. not happening.

Then the operator presses the button Per. A. From this point in time, the device is simultaneously in read and transmit mode. When this signal Per. And the trigger 40 is transferred to the state T, and the corresponding LED lights up on the indicator 38, indicating that the device is in the automatic sending mode. A logical signal 1 from the output of the trigger 40 is fed to a pulse generator 36 which starts to work and generate pulses, the period of which corresponds to the time interval between the messages transmitted to the external device. The first pulse from the output of the generator 36 is supplied through the OR element 17 to the counting inputs of the counters 3 and increases their state by one, i.e. the number of the next in order parcel is formed. This number (its binary code) determines the address of the memory location D of which the next (second) order is stored.

At the same time, the pulse from the output of the generator 36 is fed to the clock input of the trigger 37 and translates it into a single state. The logical signal 1 from the output of the trigger 37 is fed to the inputs of the elements OR 30 and 33 and then to the input 42 of the driver of 25 pulse sequences and to the input of the Strobe. devices. At the same time, the format 25 of pulse sequences generates signals similar to those formed in read counting (Fig. 4a-m). Therefore, the memory block 18 in this case is read and written to the second parcel registers 14. At the same time, the first parcel, previously recorded in registers 14, arrives at the input of the E 35 element. Since the output is Strobe. Since the device is present at the time (strobe signal), then elements 35 and 39 permit the passage of signals arriving at their other inputs to their outputs. Thus, at the exit of the Strobe. devices form a gating pulse,

at the exit, the Package is the code of the first package, and at the output is Sync. - synchronizing pulses accompanying this code message.

Upon completion of reading from block 18

the memory of the second parcel and its recording into registers 14 and transmission to the external device of the first parcel by a signal from the transfer output of counter 26, trigger 37 goes to the initial zero state. At the same time, at the outputs of the elements OR 33 and 30, as well as at the outputs of the device, the levels of logic 0 are set and the driver of 25 pulse sequences stops its operation. On indicators 5 and 10, the number and contents of the second are highlighted, respectively; the dressing that the operator observes visually.

From the moment of appearance at the output of the generator 36 of the second pulse, the described process repeats, only in this case, the external device transmits the second package, and the third package from the memory block 18 registers the third package, etc. Lna5 logically into the external one The device is transferred to other dressings.

It should be noted that the time interval between the bursts (the pulse period of the generator 36) can be changed

0 in the process of work, providing the device with the appropriate control. In this case, the specified time interval can be quite small (fractions of seconds), but should not be less than one cycle.

5 read data from memory block 18 (the trts interval in FIG. 4). If the counters 3 have N states, and the Olek 18 memory contains N memory cells for storing N packages, then depending on the content of the last N0 and the cell, the mode of automatic transmission of the packages can be single or multiple. If O is recorded in the Nth memory cell, then after the transmission (M-1), the first parcel to registers 14 will be recorded only O, the output of the OR-NOT 15 element G occurs, which allows the passage of the pulse from the transfer output of the counter 26 ( at the time of the end of the transfer of the last (M-1) -th parcel) through the element And 16 and then through

0 element OR 31 to the setup input of the trigger 40. As a result, the trigger 40 returns to the initial zero state, the generator 36 stops working and the further transmission of the parcels does not take 5 seconds, i.e. after a single transmission of all (N-1) parcels the device automatically stops. If you now again click on the button Per. And, the process of sending the group of parcels will resume and repeat, starting with the first parcel.

If the last Nth memory location contains a parcel (the data is not zero), then it is easy to see that the process of sending parcels to an external device will be carried out cyclically and repeatedly.

The operator can at any time to stop sending packages by clicking on the same Per button. A, As a trigger 40, a T-flip-flop is used, which changes its state each time with the appearance of the next impulse arriving at its clock in /; one. Therefore, if during the transmission of the group of parcels, when the trigger 40 is in one state, to press the Per, A button, the trigger 40 will go to the zero state, the pulse generator 36 will stop its operation and the transmission of the parcels will not occur. If you now again click on the button Per. And, the parcel transfer will resume exactly from the parcel which was recorded in registers 14 from the transfer stop.

Note that sequential automatic PI data retrieval to external devices can begin with any send. In the memory, the e 18 memory contains the N parcels of the operator that you can count and write to the registers 14 as any, for example the i-th, the parcel, and then performing the consecutive automatic erasure of the 1st, (And 1) and t , d. parcels.

The ability to set any base as the source and at any time stop the transfer mode, allowing the operator of the mz set of packages stored in the device's E memory to transfer to the external v device only that part of them that is needed at the moment.

Sequential transmission of a group of parcels with the participation of the operator (manual transmission mode) is as follows.

Previously, the operator puts the device into read mode, then enters the number of the original parcel into the counters. After entering the last digit of the number, the contents of the package are automatically read from memory block 18 and written into registers 14. The device is now ready for transmission.

Then the operator presses the button Per. About (before and once, successively, ruch-pch). Ex 1 this signal The jepes element 11LI 17 enters the counting inputs of counters 3 and increases their state by one, i.e., the number of the next order is generated. At the same time, the trigger 32 goes into one state. Signal a logical 1 from the output of the trigger 32 post cheoz elements OR

30 and 33, respectively, at the entrance 42 of the driver 25 and at the entrance of the Gate. devices. As a result of this, in the manner described above, the first parcel contained in registers 14, the device parcel is output by bit, and the next parcel is recorded in registers 14. Upon completion of the transfer to the external device of the first parcel and writing to the registers 14

0, a second signal is sent by the output from the transfer of the counter 25 (for example, FIG. 4), the trigger 32 is reset to the initial zero state.

The second parcel is transmitted in this mode only when the operator again presses the button Per, O. In this case, the second parcel is transmitted to the external device, and the registers 14 are recorded and prepared for transmission

0 third parcel, etc. The operator can at any (necessary) time points click on the Per button. Oh and consistently transfer to the external device all the parcels. At the same time, as in the automatic data transmission mode, an operator from a variety of parcels can transfer to the external device only that part of them that is necessary.

A single or multiple transfer to an external device at arbitrary moments of time of any of the information packages stored in the memory unit of the device is performed as follows.

5Pre-read mode

the operator enters into the counter 3 the number of the desired parcel, after which the contents of this parcel are automatically recorded in registers 14, then the operator presses the button

0 Pe h. M (transmission multiple). This triggers the trigger 34, the logical signal 1 from its output through the elements OR 30 and 33 to the input 42 of the driver 25 and to the input of the Strobe. devices. From this time on, the parcel contained in registers 14 is transferred to an external device, and in registers 14, the same parcel is recorded again. This is because the number (parcel number),

The 0 contained in the counters 3 does not change when you press the Per button. M, as was the case in the preceding cases, and the address of the memory cell from which the parcel is read does not change. At the end of the transfer cycle

5, the data and the write of the parcel to the registers 14 by the signal from the transfer output of the counter 26, the trigger 34 is reset to the initial zero state. When you press the button Per. The same parcel is transmitted to the external device, M, etc.

Thus, the operator may repeatedly send any parcel.

If it is necessary to transmit the parcels in a wrong order, in the order in which they are located in the memory block 18, this is done as follows.

First, the operator enters the number of the first parcel, after which it is read and written into registers 14. Then the operator presses the button Per. M (or Trans. O). the data parcel is transmitted to the external device. Then the operator can enter any other number of the parcel and then we can transfer this, parcel, etc.

In the process of working with the device, there may be cases when it is necessary to change the contents of one or several packages stored in the memory block. The operator can do this operatively, but not entering and not writing all the packages in the memory block again. For this, the operator presses the Enter button, as a result of which the signal of the same name goes through the OR 24 element to the setup input of the trigger 21 and transfers it to the zero state. In this case, the device enters the Input mode described above. Then the operator in a known manner carried out the input of the number of the parcel that needs to be changed, and the new content of the parcel. The operator then presses the Record button and a new package is recorded in the corresponding memory cell of the memory block 18. In the same way, the contents of any other cell of the memory block 18 can be changed. After changing the structure of some parcels, the operator can again transmit parcels to an external device.

Receiving information parcels from an external device is carried out as follows.

To prepare the device for receiving information, the operator presses the Receive button. In this case, the counters 3 and the registers 14 are zeroed out, as was described for the Input mode, and the sequential shift mode is prepared. Similarly, the distributor 7 pulses are reset to O at the moment when the Receive button is released, In addition, the Receive signal through the OR elements 24 and 31 It enters the installation paths of the flip-flops 21 and 40. This ensures that the read and (or) automatic transfer modes (if the device was in them) is reset by resetting the specified triggers to the initial zero state. At the outputs of the memory block 18 and the element AND 20 in the Receive mode, the logic level O is found and the data through the OR element 11 to the input D1 of the register 11 can only be received from an external device. At the output of the element And 47 and at the output 46 of the imager 25 is also present 0 and on the synchronization inputs C1 of the registers 14

through the element OR 13 I can) receive only synchronizing pulses from an external device. Thus, the device is ready to receive information.

Information from an external device

0 bitwise, accompanied by clock pulses, is written to registers 14 and displayed on indicator 10.

The operation of the device under consideration in conjunction with an external device may

5 occur in various modes, including interactive. Let's assume that s. using the device in question, a group of information packages is transmitted to the external device, and then the response information from the external device also comes in the form of information packages. The proposed device allows not only receiving information packages from an external device and realizing their indication in real time, but also writing to memory block i8 for storage and subsequent repeated reading and display at the request of the operator. This is done as follows.

The memory cells of the memory block 13 can be divided into two regions. The first of these records a group of information packages intended for transmission in

5, the external device, and the second record the parcels received from the external device. Beforehand, the operator enters into the counter 3 the number of the memory cell into which the first parcel will be written, received

0 from external device. After receiving the parcel, the counters 3 and registers 14 will contain, respectively, the memory cell number with the contents of the received parcel, which must be written into the data cell. This information is displayed on indicators 5 and 10.

The operator then presses the Record button. In this case, the signal Record through the element OR 8, resets the distributor 7 pulses to the initial zero state, and the received parcel is recorded in the corresponding cell of the memory block 18 (operation of the device in this mode was described above). At the end of the recording cycle

5, the trigger 19 goes into the initial state, and at the output of the element I 20 there is a logical O.

Then the operator enters into the counter 2 the next cell number of the memory block 18 to record about it the next parcel coming from the external device, f locne of receiving the second parcel, the operator presses the Record button again, etc. Thus, the device memory block can also be written - the whole Group of the SUPPLIERS WHICH GOES P, PW

him devices. These parcels are stored by the memory block for a long time.

The presence in the device of the C4 vu mode, nor the data, allows the route in the distant frame to repeatedly read these parcels from the memory block and display them on the indicator 10.

The proposed device in the pro, esse work provides an arbitrary combination of considered ix above modes of operation. So, for example, by carrying out an automatic transmission of parcels, we can do automatic transmission at any time, then resume it or switch to manual f, ef f-mode, then send some parcel to several oases, then, say, Receiving response information from i- so promptly change the so-called parcels and again carry out nepe / uti / and various wggs, | M; .x, etc. This all expands our trim ryci to arrange that ijv to see that the proposed usfopism provides and V IPO high soon, p.diii bix D vo, it known word; For example, with an automatic mode, an ordering device can be transferred to a group of posok at intervals of about a second, which cannot be provided with a known device. Transmission of parcels in other modes also offers mytmals. The number of beginnings on the controls and the corresponding time limit on the transmission of data.

Thus, the proposed carbonist, in contrast to the known device, additionally provides for recording a device memory block and storing a group of informational links of different structure; reading on request of the operager and indication of information sent in the memory block, without transferring them to the external device, sequential, single or multiple automatic (without operator's participation) transmission to the external device of all or part of the inforForg device Ia- tional parcels with a given time interval between parcels, consistent with the participation of the operator, are transferred once or several times to the external structure of all or part of those that are in the memory block of the information device. x parcels with arbitrary time intervals between the parcel and definable opin-plM, OAiiOKpaiiiyiu or multiple re-transmissions of the g / s external will arrange any jitter of any information stored in (5not eii pi y triostsz information 1 j, pni chip content) t .ogg. of information packages,

-. |. 3t and. i biuif memory; record with us in 11 JOHLTBT dt snoring and the following. - and, - ,, - h p. Duty with -.ptnivanie and oyubrazheN1-H- Grupp 1 INFORMRTSIONNYH OF EXPERTS,

Rin ch-x from D4pi4iif- (o devices; a proprietary combination at the request of the operator in oie-h modes of operation.

An al l of the specified modes of operation usb ip ii CTTia meaning heat, expanded into

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Claims (2)

Claims of the invention (} 1 chlroystvo for a gadfly-hl informational infusion, a keyboard, an encoder,  Serp i n second elengly OR control unit, impulse distributor, group | ..eister, first decoder and first 1 cable exits of the controller through the encoder are connected to the inputs of the parallel usof and registros yy; shm i. the outputs of the parallel bridge are connected via a first decoder to the input of the first The 0 indicators, the outputs of the serial output and the inputs of the sequential input of the cx ix registers of the group are combined, the synchronous inputs of the registers of the group are combined, and the strobiers panm are connected to the co5 (m), (m + n) m (where n is sliche | | parcel, am - the number of characters in; oh because) vyiodlmi distributor mg. Psop, the counting input is a cheap connection -) remove the first element OR, Q g-stroke of which is connected to the first output of the control switch, the output of which is connected to the control inputs of the group registers, connect the input of the first group register to the output B of the second element OR, the first input of which I am evil with the information input of the device. The inputs, reception, and recording of the usress Rasgva i are consistent with the first, second, and third inputs of the control unit from, characterized in that, in order to expand the use of data and transmit data to the external the account of the organization of billing modes of water and its output 5 information, it contains ipynny counters, second decoder, second and third indicators, triggers, AND elements, pulse generator, counter, pulse generator, third to eleventh elements OR OR-1 IE pulse, serial pulse generator i and memory block ti, the first, the stroke of the third element OR is connected to the input of the device Record and to the clock input of the first trigger, the output of which is connected to the first input of the pulse generator, with the first inputs of the first and second elements And a write-read memory unit whose information input is connected to the serial output of the last group register, to the first descent of the third AND element, and to the second input of the second AND element, the output of which is connected to the second input of the second OR element, the third input of which is connected to the primary input memory unit, the first group of addressable RCS of the poDs of which is connected to the outputs of the pa ° output of the output of the fuppa of the counters and through 4po (Hue; odes of oyyrykh are connected to the encoder's ipyn- output, the outputs and inputs of the transfer of counters of the group are connected in series, the counting inputs of the counters of the group are connected to the output of the OR element, the first input is connected to the fourth trigger and with the input of the pulse generator, the second input of the ninth element OR is the input The transfer is a one-time device and is connected to the clock input of the fifth trigger, the setup input of which is connected to the second input of the fifth element I, to the installation inputs of the first, fourth, sixth triggers, counter, with the second input of the pulse shaper sequence generator and with the output of the fifth OR element. the second input of which is connected to the transfer output of the counter and to the first input of the pole the second decoder to the inputs of the second indi-ate element I, the second input of which through the cagora, the second group of address inputs of an OR-NS block is connected to the outputs of the parallel output of the rupee registers, see the stroke of the sixth element AND The memory is connected to the outputs of the counter, the counting input of which is connected to the first output of the pulse sequence generator, to the second input of the first AND element, the output of which is connected to the first input of the fourth OR element, the output of which is connected to the sync inputs of the group of registers, the second input of the fourth element OR is the synchronous input of the device, the third input of the fourth element OR is connected to the first input of the fourth AND element and to the second BU / ode of the pulse former is serial, to it, the third output of which It is connected to the synchronizing input of the memory unit, the pulse generator is connected to the power supply bus of the device, and the output is connected to the first of the fifth, sixth year, and eighth elements OR, the second input of the eighth evil end OR is connected to the input Bi-od of the device, the third input of the eighth element OR is connected to the input of the Device and the second input of the sixth element OR, the output of the eighth element OR is connected to the 45 installation input of the trigger, the clock input of which is the input Read device and you / one connected with the information of the third trigger with the first descent of the third indicator and 50 with the first input of the nth element AND, which is connected to the second input of the seventh element OR g with the second input of the third element OR, the third input the input by the sixth element of the OR INPUT is connected to the setup input of the seventh trigger, the clock of which is the input of the transfer of automatic switching devices, the trigger is connected to the input of the pulses renepiTi pa and the second EAF of the third chip. the clock input of the third trigger is connected to the p output of the pulse distributor, the setpoint trigger is connected to the output of the seventh power output OR, the third trigger output is connected to the first input of the tenth element OR the second input is connected to the first one of the first OR or with the release of the fifth trigger of the tenth element of the elephers of the OR element. On the output of the fourth trigger and the fourth trigger. RFOL input of the eleventh OR element, the third input of which is connected to the fourth input of the tenth element of the OR element and the sixth trigger of the sixth trigger, the clock of which is the input of the device's multicyr transmission, the output of the encoder is connected to the second input of the first ground OR element, the output of the tenth OR element connected to the third input of the pulse sequence former, the output of the eleventh element OR is connected to the second inputs of the third and fourth elements AND, and is the output of the device Strobe, the output of the third element AND l is connected to the second output controlled by the 55 output Sending the device, output the fourth, the output of the third element OR is connected to the input of the pulse distributor, the outputs from the first to the fifth which are connected to the corresponding gate inputs of the HORROWER group, informatively the sixth element OR of which is connected with the setup input of the seventh trigger, the clock of which is the input of the transfer of automatic download devices, the trigger is connected to the input of the pulses renepiTi pa and with the second EEP of the third signal. the clock input of the third trigger is connected to the p output of the pulse distributor, the setpoint trigger is connected to the output of the seventh power output OR, the third trigger output is connected to the first input of the tenth element OR the second input is connected to the first one of the first OR or with the release of the fifth trigger of the tenth element of the elephers of the OR element. On the output of the fourth trigger and the fourth trigger. RFOL input of the eleventh OR element, the third input of which is connected to the fourth input of the tenth element of the OR element and the sixth trigger of the sixth trigger, the clock of which is the input of the device's multicyr transmission, the output of the encoder is connected to the second input of the first ground OR element, the output of the tenth OR element connected to the third input of the pulse sequence former, the output of the eleventh element OR is connected to the second inputs of the third and fourth elements AND, and is the output of the device Strobe, the output of the third element AND l is That element is the synchronization output of the device. 2. The device according to claim 1, wherein the pulse sequence generator comprises a pulse generator, a NOT element, triggers, AND elements and OR elements, the first input of which is the first input of the pulse generator sequences, the third input of the pulse sequence generator is connected to the first input of the first element AND, and to the second input of the OR element, the output of which is connected to the input of the pulse generator, the output of which is connected to the second input of the first AND element, to the first input of the second of the AND element and through the NOT element - with the clock inputs of the first and second triggers, the information input of the second trigger is connected to the power supply bus of the device, and the output is connected tz FIG. I hjTJaJTJTjnjn n. oh s TjnJT-JTJTJTJTJTJTJ iTLr g i-11-11-i g-i. 0 five with the third input of the first element I and with the second input of the second element I, the third input of which is connected to the information input and the inverse output of the first trigger, and is the third output of the pulse sequence generator, the direct output of the first trigger is connected to the fourth input of the first element I, outputs the first and second elements And are respectively the second and first outputs of the pulse sequence generator, the setup inputs of the flip-flops are connected and are the second input of the pulse generator x sequences. FIG. I Fig.Z 7 b tl ib a-l 0 jnjTJTj-iJTJiJTj e UTJTJTJOJlJTnJT ife