SU1238090A1 - Information output device - Google Patents

Abstract

The device relates to automation and computing technology and can be used to connect a computer with a telegraph channel. The purpose of the invention, a simplification of the device, is achieved due to the fact that the device contains an AND-NE element, an inverting amplifier, a counter, a clock generator, two switches and four single pulse drivers with their connections. This makes it possible to exclude a comparison unit and one decoder from a known device. 1 il. with "

Description

The invention relates to automation and computer technology and can be used to interface a computer with a telegraph channel.

The purpose of the invention is to simplify the device.

The drawing shows a functional diagram of the device.

The device contains the first decoder 1, block 2 coitrol parity, the second decoder 3, the first element And 4, the delay element 5, the encoder 6, the first 7, the second 8 and the third 9 triggers, the first 10, the second 11 and the third 12 formers of a single pulse, the first 13 and second 14 registers, the first switch 15 with elements And 16, the second switch 17 with elements And 18, the first switch 19 with elements And 20, the second switch 21 from element 1 and 22, the fourth 23, the fifth 24 triggers, driver 25 clock signals, the first element OR 2 (, counter 27, the second element lOTi 28, WTO second AND gate 29, AND-NO element 30, an inverting amplifier 31, power amplifiers 32 to amplifiers 33, tape punch 34 fourth -formirovatel 35 single pulse, the sixth flip-flop 36, inputs - outputs 37-49.

Three modes can be distinguished in the operation of the device: standby - the initial mode in which the device is in the absence of calls from the computer; functioning with a belt perforator; functioning with a telegraph channel in the absence of a belt perforator,

These modes of the device goes over in the presence of circulation from the computer.

..

In the initial state, in the standby mode, the tape perforator is turned on, the synchronization signal from the computer on the input 46 is not received. SI 1 sync pulses are cyclically received from the tape perforator, which provide information request, SI2, which serves to punch information on the tape, and PPE, marking the transportation of the tape by one step. In each cycle, SI1, entering the fourth shaper 35 of a single pulse, from its output, sets the sixth trigger 36 to the zero state, sets the fourth trigger 23 to the zero state through the element lilM 28 and in the next cycle

signals at the inputs of the element 29 and the signal from its output sets the fifth trigger 24 to the zero state. The same signal is the output signal request for information from the computer. From the inverse output of the trigger 24, through the OR element 26, the counter 27 is set to the zero state. The device circuit is in standby mode and ready to receive information from the computer.

After the arrival of a signal in a computer, the request from the computer causes the machine to place an information character code on the information inputs 37-44 of the devices that are. the inputs of the first decoder 1, parity 2 and the second decoder 3. In the first decoder 1, the received character code is converted into the character of the MTBT 2-bit code, In parity 2, the incoming parity symbol is checked. Decoder 3 determines whether the received character code belongs to the register feature in the MTK-2 code (Russian, digital, Latin) Simultaneously with the computer code of the computer issues a sync pulse. Computer address at input 46, which goes to the first input of the And 4 element. the parity of the received code at the output of the parity control unit 2 is set to a single signal that permits the passage of a clock signal through the element 4, the clock signal from the output of the element 4 is fed to the first input of the encoder 6 and passes through it at At least on one of its second, third or fourth input of information about the register feature (Russian, Danish, digital). From the output 48 of the encoder 6, the sync igpal arrives at the counting inputs of the first 7, second 8, and third 9 flip-flops and records information about the register sign from the outputs of the second decoder 3, which can occur simultaneously on only one of its outputs.

If the newly received information came with the previous register chirp, the state of the flip-flops 7 - 9 will not change and not one of the formers of 10-12 single pulses will receive a pulse at the inputs of the fourth flip-flop 23, which remains in the initial state. In the event that the register feature changes in the newly received information, the state of triggers 7-9 changes, one of the formers 10-12 triggers, which triggers the fourth trigger 2, which with a direct output signal will prepare switch 19 for switching on the second switch 17 and issuing to the punch the code of the corresponding register in the code MTK-2. From the output of the element AND 4 clock signal through the delay element 5, taking into account the time of setting the signals at the output of the decoder 6, enters the counting input of the fifth trigger 24 and the inputs of the parallel recording of the first 13 and second 14 registers, which record the information received at their inputs. Upon receipt of the sixth trigger 36 from the puncher of the signal CI2, the switch 19, which turns on the second switch 17, turns on the signal from its direct output, and the perforator 34, through the amplifier block 32, receives a code combination of the corresponding register type. After punching, the code on the tape and its transportation one step from the perforator 34, the signal SI1 is received, which

the fourth is shortened

By means of the rotator 35 and the signal from its output, the sixth trigger 3.6 is reset to the initial zero state, thereby trigger 36 through the switch switch 19 turns off the first 15 and second 17 switches. The signal from the output of the imaging unit 35 is fed to the first input of the element OR 28 and a signal from its output sets the quarter trigger 23 to the zero initial state, which by the signal from the inverted output prepares the switch 19 of the switches for switching on the first switch 15. Since 29 is not the enable signal from the inverse output of the fourth trigger 23 at the moment of arrival to its second input signal from the output of the IL.A 28 element, then from the output of the AND element 29 the signal 49 is not excited and the fifth trigger 24 remains on in a single state. In the next cycle signal

SI2 likewise reads the symbol code from the first register 13 through the first switch 15. Since after the first cycle, at the first input of the element 29, the inverse output of the fourth trigger 23 appears

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signal, plus one, then, when the perforator 34 arrives from the ribbon 34 in the second cycle of signal SI1, as described above, output 49 will be turned on at the input of element 29, which will cause the fifth trigger 24 to its initial zero state and. the device will be ready to receive the next character from the computer. When the device for displaying information from the computer via the telegraph channel in the operation with a belt hammer 34, the driver of 25 clock pulses does not participate in the operation, since the cycle time of the perforator is many shorter than the elementary parcel in the telegraph channel and the generator does not have time to form the shift cycle in the first 13 or second 14 shift registers.

The third mode of operation of the device is for outputting information from a computer via a telegraph channel of communication with a telegraph channel of communication when a tape punch is disconnected.

The fourth flip-flop 23 controls the output from its outputs and controls the operation of the clock selector 21. In the case of the arrival of a symbol with a different register sign by. with respect to the previous one, the fourth flip-flop 23 triggers, preparing the clock frequency switch 21 to read the register information code from the second register 14. With the arrival of the clock, as described above, the fifth flip-flop 24 turns over, which turns on the clock shaper 25. C. The output of the element K 22 of the switch 21 of the clock frequency of the clock frequency is fed to the shift input of the second register 14 and from the first output of this register 14 the pulses of the information recorded in the second register 14 begin to flow, which, having passed through the element IS-NE 30 and the amplifier-inverter 31, come in to; a-a communication. At the same time, the clock i®d-pulses from the output of the 25-clock mapper are fed to the counting input of the counter 27. After the eighth pulse of the eighth pulse arrives at the output of the output pulse, a short signal appears, which through the OR 26 element is set to the initial zero position, and OR 28, fourth trigger 23 is reset.

In the case of output element 29, the output signal 49 is not excited, the fifth trigger 24 will remain in the forward f excited state, and the switch 21 clock will switch the clock frequency supply to the shift input of the first register 13, from the output of which pulses will start to flow, The information on the character code recorded in the computer in the MTK-2 code, which are transmitted through the element IS-HE 30 and the amplifier-inverter 31, are sent to the telegraph communication channel. To work together, the first 13 and second 14 registers in the MTK-2 code each character of the eight-bit code must be converted in the first decoder 1 so that a stop pulse will appear on its first output, on the second output - a starting pulse, from the third to the last the eighth - impulses of the tibit combination in the MTK-2 code and at the eighth exit - a stop pulse .-

In the second cycle, counter 27 again counts eight pulses, after which it is zeroed. Only now the signal from the eighth exit of the counter 27 will excite. At the output of the element AND 29, the signal 49, since element 29 and was prepared in advance by the first input by a signal from the inverse output of the fourth trigger 23. The signal 49 of the information request from the computer sets the fifth trigger 24 to the initial zero state, thereby turning off the driver of 25 clock pulses and the scheme of the device for the output of computer information via the telegraph channel will go to the initial mode of waiting for information from the computer. When computers receive characters that do not ... have register signs, a carriage return, the second decoder 3 does not send any signals from its outputs, and therefore the encoder 6 from output 48 does not issue a strobe to sync inputs of the first 7, second 8 of the third 9 triggers and the fourth trigger 23 remains in the zero state, and the codes of these characters are output immediately from the output of the first register 13. In case the information consumer needs to have punched tapes or transmit information with a serial code r computer codes without then

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5 0 5

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it is possible, by giving a inhibitory signal zero to input 45, to disable the second decoder 3 and to receive from the outputs of the first decoder 1 a direct computer code that will be read from the outputs of the first register 13.

In the future, the operation of the device is similar to that described.

A reduction in hardware costs is achieved by excluding the third decryptor from the comparator unit.

one .

Claims (1)

Invention Formula A device for outputting information containing a tape punch, the first and second decoders, the first and second CC1-No.1, the first and second registers, a parity check block, a delay element, two AND elements, two OR elements, six triggers, and an amplifier. the outputs of which are connected to the inputs of a tape punch, characterized in that, in order to simplify the device, it contains an AND-NOT element, an inverting amplifier, a counter, a clock driver, two switches, four single pulse drivers, an output single pulse drivers are connected to the installation inputs to the 1st fourth trigger, and the inputs to the first to third trigger outputs, the synchronous inputs of which are connected to the output of the encoder, and the inputs to the corresponding outputs of the second decoder and the inputs of the first and second the deflectors and one inputs of the parity check block are the information inputs of the device group, the other input of the parity check block is the information input of the device, the first input of the first element is AND is the synchronous input of the device, the second input is connected to the output of the parity check block, and vrsod is connected to the input of the delay element and to the input of the encoder, the outputs of the group of which are connected to the information inputs of the second register group, other information inputs of which are logical inputs and zero the device, respectively, the output of the delay element is connected to the gate inputs of the first and second registers and to the synchronous input of the fifth trigger, the direct output of which is connected to the input of the clock generator and to the By the first input of the first switch, the inverting input of the fifth trigger is connected to the first input of the first OR element, the output of which is connected to the installation input. counter, the output of which is connected to the second input of the first IDN element, the counting input is connected to; the output of the clock signal generator and with the first input of the second switch, the first input of the second element OR.is connected to the output of the fourth generator of a single pulse and to the input of the installation in O of the sixth trigger, the installation input of which is connected to the first synchronous output of the belt perforator, inputs the first decoder is connected to the information inputs of the first register, the synchronous input of which and the synchronous input of the second register are connected to the outputs of the second switch, the second input of which is connected to the inverting output m fourth flip-flop, a second input of the first klgochatel and transferred to a first input of the second AND gate, the outputs of the first register are connected to data inputs The first switch, the control input of which is connected to the first output of the first switch, one output of the first register is connected to the first input of the NAND element, the second input of which is connected to one output of the second register, and the output to the input of an inverting amplifier whose output is the other outputs of the second register are connected to the information inputs of the second switch, the control of which is connected to the second switch of the first switch, the third input of which is combined with the third input of the second switch The switch and connected to the non-inverted output of the fourth flip-flop, the output of the sixth flip-flop is connected to the fourth input of the first switch, the code of the second element OR is connected to the installation input of the fourth flip-flop and the second input of the second element I, the output of which is connected to the input of the setting at the zero fifth trigger and is the device request output, the second synchronous output of the tape punch is connected to the input of the fourth single pulse former, the outputs of the first and second switches are connected to the corresponding inputs of amplifiers conductive block.