SU1684787A1 - Data input device - Google Patents

Abstract

The invention relates to computing and can be used to enter the code information of a serial code into a computer in the direct memory access mode. The aim of the invention is to expand the functionality of the device by generating the address identifier of the information word. The information input device comprises the first driver 1. data register 2, address register 3, multiplexer 4, trigger 5, interface block 6, second driver 7, indicator 8, third driver 9, shift register 10, fourth driver 11. Fourth driver 11 contains a pulse generator 12, a counter 13 and a decoder 14 The device saves the computer memory, since only the numerical part of the words without their addresses is recorded. It also eliminates the need to programmatically set the device service registers to their initial states. 1 3 P f-Ly 1 1М Ё

Description

The invention relates to computing and can be used to enter code information.

The aim of the invention is to expand the functionality of the device by generating the address identifier of the information word.

 The drawing shows the functional diagram of the device.

The device for inputting information contains the first driver 1, data register 2, address register 3, multiplexer 4, trigger 5, interface block 6, second driver 7, indicator 8, third driver 9, shift register 10 and fourth driver 11 Fourth driver 11 contains a pulse generator 12, a counter 13 and a decoder 14

The device works as follows.

The input information, which is a sequential code according to GOST-18977-79, arrives at the input of the third imager 9. Each word (parameter) in this code contains the address part — 8-bit and the number part — 16-bit. Words are separated by pauses lasting 4 bits. The input driver 9 converts a bipolar two-level successor code into a potential sequential code received through the first output of the third input generator 9 to the information input of the shift register 10. At the second output of the input generator 9, sync pulses are generated from the fourth input generator 11 and an entrance

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i dk1gg pogo register 10. in which the post-c-1tyl code of the conversion p paral- The fourth shaper 11 iniyyoT pulses P moments of pauses tvk .v in layers He works as

 (ngrl mr tch i of opoh pulses 12 n maog pulses with a frequency of trace w, I.JPM j i G1 is about twice the frequency

fii poH.rvjib (, ou. the hereditary koip M, rjp, arrive at the counting input

ghpg (.ch rm 13 but B Od of the installation of about a zero of vi vi 1yut q sync pulses When the r g psig pulses the value of

i n.iud 13 ho the moss grows more,

-and in nv "- -chk kchk he will constantly

h /, and; w, h 1 | / ronpulses At the moment i, they | D impulses are absent in those || The four periods and the value of ko, g, c1 octicles increases to eight.

 the cipher of pore 14, connected to the outputs f from g to c 13, is set to the value of the code i - mka, equal to four times. As a result, on and iiN / cde lchetsch signal, approximately, in mpr / vnr r syjii words Signal with r i.n h ifiepioio formed 11, rep. Ps. The cues HJ control inputs of registers gmchnyil 2 and addresses 3, carries out

i PVCI. l pc The contents of the shifts of the pei of the source 10 i: the first driver I into the p „1gr 2 record the number i4 -l i lol, which is right at the moment of pau-1h j (the register register is 10, and the address is

i; -, log files in low order, i register n / jpeca 3, in high bits

i) i; .MO chapio code value, set by ch- other and nefjpon former 1 j chdrool 1 Register code value

  -1 0 if |., | P 1 is the address of the memory location

ii ikoiopvr for dzhcho Oyg zzapisano with, i and chi D other 2, with this sign, g i, shaper 1

i i g, 1 cts, g:,; CTL of the computer memory, and the value of Е ™ iprrg c / Obt 1 is the retry cell of the i, 1.1, and the memory.

The P-nol of the exit of the fourth form I 11 o /, but temporarily comes on the second

 c | cgrs 5, set-up it in the single-unit MiviC cot-T, and on the control input of the second 0 | 1 thyropatsi 7 signaling signal i memory access, which IG IH I / -IHHM computer memory containing the data in the data register 2, stored in the ti / nycj1 g address register 3,

  jf-stsil from which enters the channel; IM sea mush-type 4 m Opoch res. i and o

The multiplexer L and the interface unit 6 are controlled by the output signals of the formiropylether 7. After the recording of the numerical part of the word is completed in the computer memory at the third

The output of the driver 7 is generated by Simal, which sets the trigger 5 to the zero state. Since the cycle of recording information in the computer memory is fractions of microseconds, the trigger 5 during normal operation

In operation, most of the time will be in the zero state and the O indicator, as which the LED can be used. will be off. If for any reason there is no recording

5 information in the computer memory, the driver 7 will not generate a signal at the third output and the trigger 5 will remain in one state, which is fixed by the indicator 8. The need for such monitoring is connected

0 due to the fact that the input of information on direct memory access occurs without the participation of the processor and cannot be controlled by software.

Claims (2)

Invention Formula 51. A device for entering information containing the first driver, the address register, the outputs of which are connected to the second group of inputs of the multiplexer, the first group of inputs of which are connected 0 with the outputs of the data register, and the outputs are connected to the information inputs of the blackout interface, the outputs of which are the information outputs of the device, the group of control inputs5 of the outputs of which are connected to the group of control inputs-outputs of the second driver, the gate output of which is connected to the control by the gateway of the interface, and the control output 0 created with the control input of a multiplexer, characterized in that, in order to expand the functionality of the device by forming the address-identifier of the word 5, the third driver, whose input is the information input of the device, is entered into it, the first output of the third driver is connected to the information input of the shift register, the clock input of which is connected to the second output of the third driver and the input of the fourth controller inputs addresses, data register, trigger and manager 5 the input of the second driver, the reset output of which is connected to the input of setting the trigger to zero, the output of which is connected to the input of the indicator; the first group of outputs of the shift register is connected to inputs of the data register, and the second group of outputs is connected to the first group of inputs of the address register, the second group of inputs of which is connected to the outputs of the first driver. 2. The device according to claim 1, that is, that the fourth driver contains a pulse generator, the output of which is connected to the clock input counter, the reset input of which is connected to the input of the fourth driver, and the outputs are connected with the inputs of the decoder, the output of which is the output of the fourth driver,