SU1422383A1 - Pulse duration selector - Google Patents

Abstract

The invention can be used in automated control and monitoring systems. The purpose of the invention is to expand the functionality of the selector capabilities. The Izhgul-, sov selector contains counters 2 and 3 and the speeds, register 5, pulse generator 8, decoder 9, pulse driver 12, code comparison unit 14, multiplexer 15, code converter 16. The introduction of the register 6 "of the delay element 13, the elements OR 10 and 11, and the trigger 4 allows the simultaneous selection of the pulses of the minimum and maximum duration from a series of pulses. 2 silt i.O

Description

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The invention relates to pulse engineering and automation and can be used in automated control and monitoring systems, in particular, in instrumentation equipment during the processing of information systems.

The purpose of the shadow invention is to expand the functionality by providing the possibility of simultaneous selection of minimum pulses and. maximum duration of a series of pulses.

, FIG. 1 shows a structural electrical selector circuit; Fig. 2 shows timing diagrams explaining the operation of the selector.

The pulse selector contains the initial setting bus 1, which is connected to the pre-record input of the first counter of 2 pulses and the reset input of the second counter of 3 pulses, the input of which is pre-recorded is connected to the R input of the trigger 4, and the outputs - bit by bit with information inputs of the first 5 and second 6 registers. The input bus 7 is connected to the trigger input of the generator 8 pulses, the counter outputs 2 are bitwise connected to the inputs of the decoder 9. The control inputs of the registers 5 and 6 are connected to the outputs of the corresponding 10 and second 11 OR elements, and the write inputs to the output of the driver of 12 pulses and the input element 13 is connected to the counter code 3, one bit connected to the inputs of the first group of inputs of the code comparison unit 14, the inputs of the second group of inputs — which are connected to the outputs of the multiplexer 15; the inputs of the first group of inputs of which are connected bit with register 5 outputs and inputs of the first group of information inputs of the code 16 converter in a time interval, the first and second outputs of which are connected to the first 17 and second 18 output buses, respectively, and the inputs of the second group of information inputs are bitwise with the outputs register 6 and the inputs of the second group of inputs of the multiplexer 15, the control input of which is connected to the first input of the element OR 10 and the inverse output of the trigger 45 whose C input is connected to the reset inputs of registers 5 and 6 and the reset input of the counter 3, and S input 5

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0 0 5 0 5 Q h

with the output of block 14 and the first input element OR 11, the second input of which is connected to the second input of the element OR 10 and the second output of the decoder 9, the first output of which is connected to the reset input of the counter 2 and the trigger input of the converter 16. The output of the generator 8 is connected to the counting input of the counter 3, the input of the preliminary recording of which is connected to the output of the delay element 13. The input of the driver 12 is connected to the counting input of the counter 2 and the input bus 7. The converter 16 of the code in the time interval can be implemented using two devices.

FIG. 2 shows timing diagrams: a - on the input bus 7; b - at the output of the generator 8 pulses, c. - at the output of the imaging unit 12 pulses, r-at the output of the element 13 of the droderski, d - at the output of the block 14 comparing codes, e - at the inverse output of the trigger 4, w - at the first output of the decoder 9, h - at the first output wg-1 not 17, and - on the second output bus 18,

The pulse selector by duration works as follows.

After power is turned on, a pulse is applied to the bus 1 of the initial installation, through which the first counter of 2 pulses, the second counter of 3 pulses, the trigger 4, the first register. 5 and the second register 6 are reset to the initial zero state. A series of width-modulated pulses is fed to the input bus 7. On the leading edge of the first selected pulse, the generator 8 is started up and sends pulses to the counting input of the counter 3 pulses, the number of which is proportional to the duration of the selected pulse. Pulse counter 2 also switches over the leading edge of the selectable pulse and changes the state of the decoder, at the second output of which a logic level 1 appears, which passes through the OR 10 and 11 elements to the control inputs of registers 5 and 6. On the falling edge of the first of a selectable pulse, the pulse generator B stops, and the pulse shaper 12 generates a short pulse, through which the code with punctures is sent to registers 5 and 6

pulse counter 3, then this pulse passes through delay element 13 and sets pulse counter 3 and trigger 4 to the initial zero state, but registers 5 and 6 store a code proportional to the duration of the first selectable pulse. The second selectable pulse starts the generator of 8 pulses and the code begins to change at the outputs of the pulse counter 3. This code arrives at the first group of inputs of block 14 of code comparison, and the second group of inputs of this block through the multiplexer 15 receives a code from register 5 proportional to the duration of the first pulse. In block 14, code comparisons compare a code proportional to the duration of the first pulse, and a code proportional to the duration of the second pulse.

If the duration of the second pulse is less than the duration of the first pulse, then a code proportional to the duration of the second pulse is written to the register 5, to the enabling input of which the logical level 1 from the output of trigger 4 goes through the element OR 10. ..,

If the duration of the second selectable pulse is greater than the duration of the first pulse, then at the output of the code comparison unit 14 a positive signal appears, which triggers switch 4, the signal from the enable input of register 5 is removed and the multiplexer 15 switches to the second group of block inputs 14, a code from register 6, proportional to the duration of the first selectable pulse, arrives. At the output of the code comparison unit 14, the logic level 1 is maintained, which through the OR 11 element arrives at the enable input of the register 6. On the falling edge, the second of the selectable pulse stops the pulse generator 8, and the pulse driver 12 generates a short pulse, according to which the register 6 is written to register 6 The proportional duration of the second selectable pulse then this pulse passes through the delay element 13 and sets the counter of 3 pulses and the trigger 4 to the initial zero state. Thus, in register 5 is stored a code with a length of 5

d

five

0

0

five

0

five

0

five

The pulse length of the pulse is of the minimum duration, and in the register 6 there is stored a code proportional to the pulse duration of the maximum duration of the first selectable pulses.

If the third pulse is less than the pulse of the minimum duration of the first two pulses, the code proportional to the duration of the third pulse is written to register 5, to the enabling input of which a positive signal is output from the output of trigger 4,

If the third selectable pulse is longer than the pulse of the maximum duration of -13 first two pulses, then the code is proportional to. The national duration of the third pulse is recorded at 6, the Control input of which receives a positive signal from the output of the code comparison block 14.

If the third selectable pulse is longer in duration than the pulse of the minimum duration of the first two pulses, but less than the pulse of the maximum duration of the first two and fflyls, then the code is proportional to the duration of the third; the pulse is not recorded either in register 5 or in register 6, because the code comparison block 14 switches trigger 4 and removes the logic level 1 s. the control input of register 5, there is no logical 1 and the control input of register 6.

Further, the code proportional to the duration of the next selected pulse is compared first with the code, proportional to 1; ional for the minimal impulse from the previous ones, which is stored in register 5, and the smallest of them is stored in register 5. If the code rtponoptional for the duration of the next pulse, greater than the code proportional to the duration of the minimum pulse from the previous ones, then it is compared to the one proportional to the duration of the maximum pulse from the preceding 1гх, which is c in register 6, and One of them is remembered in reg 1str. 6.

Thus, after the end of a series of selections Pye rc, Ix pulses, in register 5 xpamiTCH, the code is proportional to the pulse length D of the shortest duration from a series of pulses, and in register 6 the code is proportional to the maximum duration of the pulse from the pulse series and the converter 16. of the code, in the time interval, repeats on the output bus 17 a pulse of the minimum-: But duration, -a pulse of the maximum duration repeats: on the output bus 18.

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Pulse selector by duration, containing a pulse generator, the triggering input of which is connected to the input bus, with the input of the pulse former and the counting input of the first pulse counter, and the output with the counting input of the second pulse counter, whose codes are one bit connected to the inputs of the first group of inputs of the comparison unit codes, and the input: the reset is connected to the input of the preliminary record of the first impulse counter, whose codes are bitwise connected to the inputs of the decoder, the first output of which is connected to the reset input the first pulse counter and the trigger input of the code converter in the time interval, the first output of which is connected to the first output bus, the output of the driver, the pulses are connected to the recording input of the first register, the codes of which are connected to the inputs of the first group of multiplexer inputs, differing in that, in order to extend the functionality by providing the possibility of simultaneous selection of them

pulses of minimum and maximum duration from a series of pulses, a delay element, the first and second elements OR, a trigger, a second register, a second output bus and an initial installation bus, which are connected to the reset inputs of the second pulse counter, the first and second

registers and C-input trigger, RVhrd which is connected to the input of the pre-. Alternate recording of the second pulse counter and through the delay element with the output of the pulse driver and the recording input of the second register, the inverse OUTPUT with the first input jiepBoro of the OR element and the control input of the multiplexer, and the S input with the output of the code comparison unit and

the first input of the second et1; ement OR, the second input of which is connected to the second input of the first element S1I and the second output of the decoder, the outputs of the first AND second elements OR are connected to the control inputs of the first and second registers, respectively, the information inputs of which are bitwise connected to the outputs of the second pulse counter, the outputs of the first register. The bit is connected to the inputs of the first group of information inputs of the code converter. In the time interval, the second output of which is connected: to the second output line hydrochloric, and c vhody.vtoroy uppy informatsionnk bitwise inputs connected to outputs of the second register and the second inputs grzshpy multiplexer inputs, the outputs of which are connected bitwise with the inputs vtopoy

groups of block comparison block inputs.

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Claims (1)

A selector containing a pulse generator, the starting input of which is connected to the input bus, with the input of the pulse shaper and the counting input of the first pulse counter, and the output with the counting input of the second pulse counter, the outputs of which are bitwise connected to the inputs of the first group of inputs of the code comparison unit, and the reset input is connected to the preliminary recording input of the first pulse counter, the outputs of which are bitwise connected to the inputs of the decoder, the first output of which is connected to the reset input of the first pulse counter and triggering input of the code converter in the time interval, the first output of which is connected to the first output bus, and the output of the driver. pulses connected to the recording input of the first register, the outputs of which are bitwise connected to the inputs of the first group of inputs of the multiplexer, characterized in that, in order to expand functionality by providing the possibility of simultaneous selection of