SU955205A1 - Device for read only memory electric programming - Google Patents

Description

The invention relates to memory devices and can be used to automatically enter information into a semiconductor memory device by burning through fused jumpers and monitoring the information entered. A device for electrical programming of blocks of permanent memory is known that contains schemes for selecting the appropriate word address (word line) and the corresponding information bit (jumper address) and current generator, the output of which is connected to the selected jumper 1. The disadvantages of this device are low speed and reliability. Of the known devices, the closest technical solution to the present invention is a device for electrical programming of a block of permanent memory, containing an operative memory (RAM) with a capacity of 4096 12-bit words, for storing a control program and truth table, in accordance with where information is entered, corresponding to (equivalent) to the reference ROM unit, automatic address setting unit, comparison circuit, command signal generation circuit for burning, emptying block Ananova and synchronization, a static parameter meter containing programmable voltage and current sources and a test panel for connecting a programmable circuit to the dongle keys and to address circuits, I / O and interface units. 2. The disadvantages of this device are its complexity and the impossibility of automatically setting the duration of the effect of a burning pulse, depending on the time required for burning through the jumper, which reduces its speed and reliability. The purpose of the invention is to increase the reliability and speed of the device. The goal is achieved by the fact that the device for electrical programming of the blocks of the fixed memory, which contains the bit selection unit, the address register, the pulse shaper, the control pulse shaper, the bit keys, the standard setting unit, the first comparison circuit and the local control unit, the output of which is connected to the counting bit selection unit, the first clock of which is connected to the counting input of the address register, one of whose outputs are connected to the inputs of the set of reference samples, the first control input block estno control connected to the control input of the current and the Dulce and bit keys od. whose inputs are connected to the second output of the block, respectively, the choice of bits with the outputs of the standard setting block and one of the terminals of the first comparison circuit and the output of the current pulse driver whose input is connected to the first output of the control pulse former, one of the outputs of the address register and others the inputs and outputs of the bit switches are respectively the address outputs, the bit inputs and outputs of the device, the current pulse duration sensor, the AND-OR element and the key are entered, the first: the output of which is connected to W the neutral potential, the input to the second output of the driver of control pulses, and the second output to the control input of the driver of pulses, one of the inputs of the AND-OR element is connected to the output of the bit selector and one of the current pulse duration sensors, the other inputs of which are connected to the other inputs of the first comparison circuit and other outputs of the bit switches, other inputs of the AND-OR element are connected to the outputs of the task setting unit, and the output is connected to the first input of the control pulse generator second input and third output the stroke of which is connected respectively to the output and to the first control input of the current pulse duration sensor, the second control input of which is the input reference voltage of the device, the output of the first comparison circuit is connected to the second control input of the local control unit, the installation input of which is connected to another output of the address register. The block control contains Triggers, an OR-NOT element, AND elements, an NOT element and a delay element, the output of the OR-NOT element is connected to the input of the first NO element, the output of which is connected to the first input of the first AND element and the reset inputs of the first and second triggers. , the second input of the first element AND connect to the output of the second element NOT and the blocking input of the second trigger, which is connected to the blocking input of the Third trigger, the reset input WHICH is connected to the output of the first element AND, and the counting input to the counting input of the second trigger and the output of the third element is NOT, the input of which is connected to the first input of the second element. And, the second input and output of which are connected respectively i STB8NN-O to the output of the first trigger and the first input of the first AND-NO element, the second input i oToporo is connected to the output of the third trigger, and the output to the input of the delay element, counting input of the fourth trigger and the input of the fourth element is NOT, the output of which is connected to the first input of the second element NAND, the second input of which is connected to the output of the fourth trigger, the first input of the third element NAND is connected to the output of the delay element, and the output to the first input of the element OR NOT, the second entrance is koto It is connected to the reset input of the fourth trigger and is the reset input of the block, whose Start input is the installation input of the first trigger, the third and fourth inputs of the OR-NOT element and the input of the second element1 are NOT the installation and control inputs, the second input of the third The AND-NAND element, the input of the third element NOT, and the output of the second element AND-NAND are respectively a stop enable input, a clock input and a block output. FIG. 1 shows a functional diagram of the proposed device; in fig. 2 and 3 are functional diagrams of the most preferred embodiments of the local control unit and the current pulse duration sensor, respectively. The device contains (Fig. 1) a local control unit 1, a block, 2 bits selection, an address register 3, a current pulse shaper 4, a discharge key 5, a fixed memory block, into which information is entered, a control pulse shaper 7 , the element AND-OR 8, the unit 9 for setting standards, the first comparison circuit 10, the sensor 11 for the duration of current pulses and the key 12. In FIG. Figure 1 denotes the input 13 of the device's reference voltage, the installation input 14, the input 15 clock pulses, the output 16, the first 17 and the second 18 control inputs of the Local Control unit. At the same time, the local control block contains (FIG. 2) an element OR-NOT 19, the first 20, the second 21, and 22 and the fourth 23 NOT elements, the first 24, the second 25 and the third 26 AND elements, the first trigger 27, the first 28 and the second 29 elements And the delay element 30 with the output 31, the second 32, the third 33 and the fourth 34 triggers. In FIG. 2, the inputs are marked Start 35, reset 36, and block stop enable 37. The current pulse duration sensor is designed to monitor the time during which full fusing of jumpers occurs, and contains (Fig. 3) a voltage divider 38, a second comparison circuit 39, the first 40 and second 41 groups of elements AND according to the number of controlled bits of the block constant memory and the element OR 42; FIG. 3, a third sensor input 43 is designated for a strobe signal.

The device operates in two modes of recording information and control.

The mode of entering information. The Start command unit 1 (Fig. 1) generates a command signal, synchronous with the clock frequency received at the input 15 (Fig. 1. and Fig. 2). The first command signal does not pass to the input of the block. 2 (Fig. 1), which corresponds to the preservation of the initial state. The code from block 2 is decrypted and fed to the inputs of the keys 5 of the element AND-OR 8 and the sensor 11. The presence of a signal at the first output of block 2 corresponds to the selection of the corresponding bit of the memory block b. The inputs of the AND-OR 8 element receive signals from the outputs of block 9. The coincidence of the signals in the AND-OR element 8 coming from the outputs of block 2 and block 9 corresponds to the availability of information and an indication of the jumper jump in the memory block b. On a command at output 31 of block 1 (Fig. 2), arriving at one of the inputs of the AND-OR 8 element (Fig. 1), a signal appears at its output that triggers the driver 7, which generates a signal to start the driver 4 and a control signal which, through the key 12, is fed to the input 17 of block 1 and the control inputs of the imaging unit 4 and the keys 5. The signal at the input 17 (Fig. 1) prohibits the generation of command signals during the jumper burnout time. The signals at the control inputs of the keys 5 and the driver 4 allow the passage of a current pulse to the input of the memory block b. Codes from the outputs of block 2 and block 9 are fed to the keys 5 and control the selection of the required bit of block 6. Simultaneously with the sending of a current pulse through the keys 5, a burnout voltage is monitored, which increases as the jumper is burned out. When the jumper is broken, the burn-up voltage reaches a maximum value.

Sensor ll monitors this voltage and when the voltage reaches the reference level set by input 13 and the presence of a strobe pulse at input 43 (Fig. 3) produces a signal that starts the driver 4 (Fig. 1), the signal of which limits the command time a signal from the first output of the imager 7, the duration of which is determined by the length of the jumper burnout time. At the second output of the driver 7, the control signal is present for the time required to burn out the jumper and cool the circuit. On this the loop jump cycle ends. The inhibitory potential is removed from the first control input 17 of block 1 and linked to a clock frequency. Add unit in block

2 (FIG. 1), which corresponds to the choice of the third digit of the zero address. If a

in the second section of block 9 (Fig. 1), single information is recorded, then the jumper is burned out

the same way.

If the zero information is recorded in block 9 for this bit, then there is no need for burning and the AND-OR element 8 (Fig. 1) does not produce a trigger pulse at its output, and the operation of block 1, which gives a pulse to block 2, is not prohibited which corresponds to the choice of the next bit address, and the operation continues.

In those bits where there is no information to record, the bit overflow occurs with a clock frequency (the clock frequency can be 1 MHz for the element base, for example,

KM155 series, and in those places where the information is located, burning is performed taking into account the necessary mi-. minimum time, which depends on the manufacturing technology (size

jumper) and, as a rule, has a 50% variation.

After busting; all bits and addresses from the output of the register 3 to the input 14 (FIG. 1 gives a signal that stops the operation of the device.

In the output control mode, the switch 12 is connected to the zero potential bus. The signal at control input 17 enables polling at a clock frequency and blocks the operation of the driver

4 and the keys 5. The read codes of the two bits of the block, 6 and block 14 are compared in scheme 10 and the absence of an error is permitted to change the address. If there is an error

stop, the result of the mismatch is indicated (indication circuits not shown). After a restart, the control is continued. At the end of monitoring, all addresses are automatically stopped.

Technical and economic advantages of the proposed device in comparison with the prototype consist in the fact that it provides control over the time of burning the jumpers in blocks of the CONSTANT memory with a significant reduction in equipment, which increases its reliability and speed.

Claims (2)

1. A device for electric programming of a fixed memory block comprising a bit selection unit, a register of stills, a current pulse shaper, a control pulse shaper, bit keys, a standard task block, a comparison circuit and a local control block whose output is connected to the counting the input of the bit selection unit, the first output, which is connected to the counting input of the address register, one of the outputs of which is connected to the inputs of the standard setting unit, the first control input of the local control unit, is connected equaling inputs of current pulse generator and bit switches, one of the inputs of which are connected respectively to the second output of the bit selector block, to the outputs of the standard setting block and one of the inputs of the comparison circuit, and to the output of the current pulse former, which input is connected to the first output of the driver The control pulses, one of the outputs of the address register and the other inputs and outputs of the bit switches are respectively address outputs, bit inputs and outputs of the device, characterized in that: for the purpose of reliability and speed of the device, it contains a current pulse duration sensor, an AND-OR element and a key, the first output of which is connected to the zero potential bus, the input to the second output of the control pulse generator, and the second output to the control input of the current pulse generator , one of the inputs of the AND-OR element is connected to the output of the bit selection unit and one of the inputs of the current pulse duration sensor, the other inputs of which are connected to other inputs of the comparison circuit and the other outputs of the bit switches, the others in the moves of the AND-OR element are connected to the outputs of the standard setting unit, and the output is connected to the first input of the control pulse shaper, the second input and the third output of which are connected respectively to the output and the first control input of the current pulse duration sensor, the second control input of which is the input voltage of the device, the output of the comparison circuit is connected to the second control input of the local control unit, the setup input of which is connected to another output of the address register. 2. The device according to claim 1, characterized in that the local control unit contains triggers, an OR-NOT element, AND elements, an NOT element, and a delay element, and the output of the OR-NOT element is connected to the input of the NE element NO whose output is connected to the first the input of the first element And the reset inputs of the first and second triggers, the second input of the first element And is connected to the output of the second element KE and the blocking input of the second trigger, the output of which is connected to the blocking input of the third trigger, the reset input of which is connected to the output of the first element This And, and the counting input to the counting input of the second trigger and the output of the third element is NOT, the input of which is connected to the first input of the second element And, the second input and output of which are connected respectively to the output of the first trigger and the first input of the first element AND NAND, the second input which is connected to the output of the third trigger, and the output to the input of the delay element, the counting input of the fourth trigger and the input of the fourth element NOT, the output of which is connected to the first input of the second element NAND, the second input of which is connected to the output fourth About the trigger, the first input of the third AND-NO element is connected to the output of the delay element, and the output to the first input of the OR-NOT element, the second input of which is connected to the reset input of the fourth trigger and is the reset input of the block whose Start input is the installation input of the first the trigger, the third and fourth inputs of the OR-NOT element and the input of the second element are NOT the installation and control inputs of the block respectively, the second input of the third AND-NO element, the INPUT of the third NO element and the output of the second AND-NOT element are respectively one stop enable, clock input and block output Sources of information taken into account in the examination 1.Souchek B. Micro-computer. M., Sov. Radio, 1979, p. 59, 60. 2.L Bin V.I. and others. Programming and control of ROM. - Electronic industry, 1976, № 4-, p. 64-67 (PROTOTYPE). 15