SU1126930A1 - Consecutive analysis device - Google Patents

Description

1 The invention relates to automation and computing and can be used for the sequential analysis of the results of counter various objects. The closest technical solution to the invention is a device for sequential analysis, comprising a first reversible counter, connected by a summing input to a terminal for receiving reject signals, exits to the information inputs of the first decoder, a counter divider, a second decoder, a second reversing counter, an auxiliary counter, the trigger, the first to fourth elements AND f1 1; A disadvantage of the known devices is the low reliability due to the significant number of elements, namely the four elements AND , trigger, and second reversible counter. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that in a device for serial: analysis, containing a roaring counter, connected sumt-shrujuprm input to a terminal for receiving marriage signals, exits - to informational inputs of the first decoder, counter-divider, the second decoder, the first and second elements OR, the prohibition element, the single pulse shaper, the switch, the display unit are introduced, and the single pulse shaper is connected by an input through the switch to the power terminal, and the output to the RELAYED setting inputs and the reverse counter and the first input of the first element OR connected by the second input to the output of the prohibition element, to the first input of the second OR element and to the subtracting input of the reversing counter, output to the installation input of the counter-divider l, connected by the counting input to the terminal for receiving signals about the number of tests and with the gate input of the second decoder connected by information inputs with the outputs of the counter-divider, the output with the non-inverting input of the prohibition element, the inverting input of which is connected to the sum a reversible counter input and a second 0 input of the second OR element connected to the CIRCULATED CHEM INPUT of the first decoder connected by the outputs with the corresponding inputs of the display unit i. The drawing shows a block diagram of the device. The device contains a terminal 1 for receiving signals about the number of tests, a terminal 2 for receiving signals about rejects, tires 3 and 4 for transmitting signals about the intersection of the lower limit n and the upper limit of decision making area t, the reversible counter 5, the first decoder 6, the counter divider 7, second decoder 8, first element 9 OR, single pulse shaper Yu, second element It 1-SHI, prohibition element 12, indication unit 131, switch 14, power terminal 15. The device works as follows. When the switch 14 is turned on, the power supply from the terminal 15 is fed to the input of the driver 10, which forms a single pulse of a predetermined duration. The impulse from the driver code to through element 9 OR is fed to the input of the installation in the zero state of the counter-divider 7, which under the influence of this signal is set to the initial (zero) state. At the same time, the same single pulse is applied to one or more of the inputs of the one-bit installation of the reversing counter 5. The inputs to which this setup signal must be applied are determined depending on the required value of the parameter b. For example, for | b | And the setting signal from the output of the processor 10 will bring the trigger of the 3rd bit of the counter 5, i.e. counter 5 is set to the position corresponding to digit 4 in the binary number system (O is supplied to the remaining inputs of the serial installation),. After setting the counter-divide 7 to the zero position and the reversible counter 5 to the position with the code / b / the device is ready to receive the input signals. During the operation of the device at each carried out extinction, the object’s counter-rnpyebjro postalega

signal from terminal 1; If a defect is detected during the test, then an input signal from terminal 2 is also received. The signals from terminal 1 act on the counting input of separator 7, which counts the number of these signals. Used in connection with counter 7 of decoder 8, only one output is activated, namely, with sequence number h,. Then, as counter 7 receives n, j signals from terminal 1, the trailing edge of the last of these signals is received from the prohibiting input of the decoder 8 and a signal appears at its output with the sequence number P o. This signal is fed to the installation input of the element 12 of the ban. On the falling edge of the signal from terminal 2, it removes the signal from the prohibitive input of the element 12, and a signal is generated at its output that acts on the subtractive input of the reversible counter 5, due to which one is subtracted from its content. At the same time, through the 1t element OR, the signal is sent to the forbidding input of Topal 6 and through the element 9 OR to the input of the counter-divider 7 to the zero position. After the passage of the counter 7 to this position, the signal from the output h of the decoder 8 is removed, therefore, the signal from the output of the prohibition element 12 is stopped. The lifetime of the signal at the output of element 12 is equal to the total delays of elements 9,7,8 and 12. This is enough time for the counter to sense the 5 pulse received at its subtracting input. After stopping the signal from the output of element 12 through element 9 OR, the return counter of divider 7 is ready to execute the new cycle of counting the signals on the number of tests sent to input 1. Thus, the counter divider 7 provides the division by the frequency of the signals coming from terminal 1. If n tests were carried out (i.e., l signals were received at terminal 1 and the counting input of counter 7), then the sub-input of the reversing counter 5 increases the value of the signals. When a defect is detected during a test, a signal is sent to terminal 2, from where

to the summing input of the reversible counter 5, to the contents of which one is added. At the same time, through element 11 OR, a signal is sent to the inhibitory input of the decoder 6. If terminal 2 receives m signals of a defect, then m units will be added to counter 5.

If in the course of conducting n tests, m cases of marriage were revealed, then in a reversible counter. 5, the code / b /, stored before work, is added m units and subtracted p / Units, i.e. counter 5 stores the code of the number V i On the falling edge of the signals from terminal 2, the input through the element 11 OR signal to the forbidden input of the decoder 6 stops, and on one of the outputs of the decoder 6 there appears a signal indicating the state of the counter 5. If a code is written to the reversible counter 5, then a signal at the output of the signal from terminal 2 appears at the output of the depressor 6 signal. The output signal yt goes through bus 4 to block 13, which indicates that the upper boundary of the decision area has crossed will follow celine analysis. Substituting the value in the expression (1), we determine the number of cases of rejection, m m g, d, at which a signal is received via the bus D about the intersection of the upper limit, i.e. about the poor quality of the control object (2) During the operation of the device, the reversible counter 5 goes to the zero position (), then at the moment when there are no signals at the counting inputs of this counter, the output signal O of the decoder 6 appears, which means crossing the lower boundary of the received area These solutions are given via bus 3 to block 13, which in this case fixes the good quality of the monitored object. By substituting the value into expression (1), we determine the allowable number of cases of rejection t-t at which block 13 gives the signal & the water quality. - / Expressions (2) and (3) make sense for the values, n, for which O, Values r and d, obtained using these expressions, should be rounded to an integer (since the number of cases of marriage may be only integer.) The indicated parameters of the device b, n and lte are determined on the basis of the generally accepted initial parameters of the method of sequential analysis (P f Pj, o (and / ь) according to the following Aormulas, where P is the largest fraction of rejects in which a controlled party of objects is taken} the smallest value of the proportion of cases of brdka, with: naiJT HH rejects C and - respectively, the probability of errors of the first and second kind (the risk of the supplier and the risk of the consumer). Formulas (4) - (6) are obtained from the basic Wald equations for the boundaries of t-2. For a specific implementation of the device, counters 5 and 7, decoders 6 and 8, and logical elements 6, 11, and 12 can be used with standard integrated circuits Shaper 10 of a single The pulse is implemented by a circuit containing a resistor and a capacitor. The inputs of the one set counter 5 and the outputs of the decoders. 8 and 6 are used in accordance with the required values of b, Пд and Згт1, which are calculated using formulas (4) - (6), from the usual criteria of P., P, ot and / i of the method of sequential analysis. Thus, in the device, unlike the prototype, the shaper 10 of a single I1 pulse, elements 9.11 OR, prohibition element 12 are entered, but there is no upper limit control block containing a reversible counter, a trigger and four elements I. By reducing the number of elements, simplification is achieved and therefore increasing device reliability.

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Claims (1)

DEVICE FOR SEQUENTIAL ANALYSIS, containing a reversible counter connected by a summing input to a terminal for receiving reject signals, outputs - with information inputs of the first decoder, divider counter, second decoder, characterized in that, in order to increase the reliability of the device, they are inserted into it, the first and second elements of OR, the element of prohibition, the shaper solo-. a pulse, a switch, an indication unit, and the single pulse shaper is connected by an input through a switch to a power terminal, by an output - with the discharge setting inputs of a reversible counter and with the first input of the first element. OR connected by the second input to the output of the inhibit element, with the first input of the second OR element and with the subtracting input of the reverse counter, output - with the installation input of the divider counter connected to the terminal for receiving signals about the number of tests and with the gate input of the second decoder connected by information inputs to the outputs of the counter-divider, the output is a non-inverting input of the inhibit element, the inverting input of which is connected to the summing input of the reversing counter and to the second input of the second of the OR gate connected to the output strobe input of the first decoder coupled to outputs of corresponding conductive frQ inputs of the indication unit. > 1 126930