RU2024906C1 - Device for the tolerance control of time intervals - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: device has shaper 1, reference signal generator 2, pulse counter 3, unit 4 of the code evaluation of the pulse counter, information processing unit 5, pulse shaper 6 by the end of the time interval, delay lines 7,8, OR element 9, shaper 10 of signals by edges; unit 4 consists of comparator units 11, 12, code formers 13, 14, OR element 15,16,17, NOT element 18, AND elements 19,20,21 and switches 22, 23. EFFECT: improved control of the time interval length and the sample time of memories. 1 dwg

Description

 The invention relates to instrumentation and can be used in devices for tolerance control of the duration of time intervals, including the time of sampling memory.

 Known devices for tolerance control of time intervals, for example, devices according to ed. N 1298708, N 1449967. These devices are unsuitable for monitoring the memory access time, since when monitoring the memory access, the time interval between accessing the memory and the appearance of information at the output of the information category of the memory can be extended due to the absence of a logical unit of information for this category, and this will lead to a false measurement of "above normal".

 Closest to the claimed is a device (ed. St. N 1449967), which contains an input driver, a reference signal generator, a counter, two summing units, two groups of inverters, an information processing unit (BOI), a pulse former at the end of the time interval, three elements delays, input bus, set bus group, write bus and reset bus. Two summing blocks and two groups of inverters can be called a counter code evaluation unit, since this block generates a signal about the value of the counter code for the BOI. The input bus, input driver, generator, counter, counter code evaluation unit, BOI are connected in series. The first and second blocks of summation by the first groups of inputs are connected to the output of the counter, and the second groups of inputs are connected respectively to the first and second installation buses via blocks of inverters. The outputs of the overflow of the summing units are connected respectively to the first and second information inputs of the information processing unit. A pulse shaper and three delay elements are connected in series to the second output of the input driver. The output of the third delay element, in addition, is connected to the inputs of the summation of the first and second blocks of the summation. The output of the second delay element is connected to the input "analysis" of the information processing unit. The output of the first delay element is connected to the bus "reset" and the inputs of the installation in the initial state of the counter and the summing units.

 This device, as mentioned above, cannot be used to control the selection of memory without additional devices.

 It is well known that reading memory information occurs as follows.

 The device receives a parallel code of the address signal and an access (polling) signal, and the address code is ahead of the access signal along the rising edge. The most significant bits of the address code are decrypted. The signal with the decoder includes in the ROM the power of a specific microcircuit or group of memory microcircuits, and in RAM it allows the output of information from a microcircuit or a group of memory microcircuits. An address code and an access signal are sent to the memory microcircuits through the input shapers. According to the reversal signal (we denote it for short OP), an information signal appears at the output of the memory microcircuit, which is transmitted through the output drivers to the output of the device. The delay of the leading edge of the information at the output of the device relative to the leading edge of the OP signal at the input of the device — sampling time — is an important technical characteristic of the device under control. Sometimes it is necessary to determine the sampling time relative to the address signal at the input or relative to the inclusion of the supply voltage. There may be some differences in the operation of a particular memory device from the above description. However, to control the sampling time, it is always necessary to control the time interval between the beginning of the signal at the input and the beginning of the information signal at the output of the device according to the category of information. Upon subsequent access to the memory, there may be no change in information on the controlled discharge. Moreover, in the prototype, the operation of the generator will continue until a high level is received via the information bus, which will lead to the appearance of a false signal “more than normal”. It is assumed that the input driver is made in the form of a trigger cocked by the beginning of the OP pulse into the state of the logical unit, and by the beginning of the pulse of the output information of the memory set to the logical zero state.

 It should be noted that the representation of the time interval in the form of a pulse duration or the time between the beginnings of two pulses arriving in two circuits is equivalent, since it is possible using simple means to switch from one representation to another.

 The purpose of the invention is the expansion of the functionality of the device, expressed in the provision of tolerance control of the sampling time of the memory.

 This goal is achieved by the fact that in the device for tolerance control of time intervals containing a first input bus, an input driver, a reference signal generator, a pulse counter, a pulse counter code evaluation unit and an information processing unit, a pulse former at the end of the time interval, the first and second delay lines, an OR element and a signal shaper along the edges of the pulse are introduced, and the pulse counter code evaluation unit contains the first and second code generator, first, second and third elements OR, element NOT, first, second and third elements AND, first and second switches, first and second comparison units, the first inputs of which are connected to the outputs of the first and second code generators, the first and second outputs comparison blocks are connected to the inputs of the first and third OR elements, and the inputs of the second OR element are connected to the third outputs of the comparison blocks, the output of the first OR element is connected to the first input of the first AND element, the output of the second OR element is connected directly directly to the first input of the second AND element and through the first switch to the input of the NOT element, the output of which and the output of the third OR element are connected to the second and third inputs of the third AND element, the output of the first AND element through the second switch, and the outputs of the second and third AND elements are directly connected to the corresponding inputs of the information processing unit, the third inputs of the elements AND are combined and connected to the output of the first delay line, the output of the second delay line is connected to the input "reset" of the pulse counter, the outputs of which are connected inens with the second inputs of the first and second comparison blocks of the pulse counter code evaluation unit, while the second input of the input driver is connected to the output of the OR element, the first input of which is connected to the output of the signal driver at the edges of the pulse, the input of which is connected to the second input bus, and the second input The OR element is connected to the input of the NOT element of the pulse counter code evaluation unit.

 The drawing shows a functional diagram of a device for tolerance control of time intervals.

 The device comprises a serially connected input driver 1, a generator 2 reference signals, a counter 3 pulses, a unit 4 for evaluating the code of the pulse counter and a unit 5 for processing information about the duration of the time interval, serially connected driver for 6 pulses at the end of the time interval, the first delay line 7 and the second line delay 8, the output of which is connected to the counter reset input 3, an OR element 9, the output of which is connected to the input of the driver 1, and the first input is connected to the output of the signal driver 10 pulse, block 4 evaluates the code of the pulse counter contains comparison blocks 11, 12, shapers code 13, 14, elements OR 15, 16, 17, element NOT 18, elements AND 19, 20, 21, switches 22, 23, the first and second input buses 24, 25.

 The device operates as follows.

 When connecting the input of the inverter 18 of block 4 to the zero bus using the switch 23 and connecting the output of the And 19 element to the input of the block 5 less, using the switch 22 the device works the same as the prototype. In this case, the driver 1 (for example, a trigger) is set to a state that allows the generator 2 to work with a signal on the bus 25, and when the state changes on the bus 24, the driver 1 inhibits the operation of the generator 2. When an impulse arrives on bus 24, signals are generated along the edge of the pulse and the decay of the pulse. The number of reference signals of the generator 2 is calculated by the counter 3 and on the comparison blocks 11, 12 is compared with the numbers installed on the shapers code 13, 14. On the shapers code 13, 14 are set the numbers corresponding to the minimum (shaper 13) and maximum (shaper 14) duration values time interval. The result of comparing the set and actual codes at the end of the time interval with a delay on element 7 goes to block 5. The limit values of the time code are conditionally accepted as unacceptable, since usually with acceptance tests devices with electrical parameters equal to the limit are rejected.

 It is advisable to combine control of the time of sampling the memory (or carry out after) with the control of information of the memory. The information of the memory is monitored in one of the following ways: by comparison with a standard, by calculating checksums, by determining the signature. The information of the memory is recorded in the control equipment by a gating signal, let's call it ST. The ST signal is supplied at a steady-state value of the memory information and its delay with respect to the OP is known to be longer than the sampling time, the difference provides a margin of operability of the memory when changing operating conditions and aging. If the device complies with checksums (standard, signature), the sampling time cannot be more than the delay time of the ST signal, but nothing can be said about the existence of the necessary health reserves, i.e. about the correspondence of the sampling time to the set value.

 Changing the temporal position of the CT signal in order to indirectly control the sampling time is not always possible, as it can disrupt the performance of the control equipment or lead to its significant complications. In addition, the CT signal indirectly checks for the absence of interference at a given point in time, therefore, the temporary position of this signal during monitoring should correspond to the normal operation mode.

 From the foregoing, it follows that the sampling time of the memory must be checked to the maximum and that the real sampling time, when the device information is set, cannot be greater than the delay of the CT signal.

 To control the sampling time of the memory switches 22, 23 must be installed in accordance with the drawing, i.e. to the position opposite to the previously indicated. On the shaper code 13, you must set the number corresponding to the delay, which is not less than the delay of the signal CT from the leading edge of the signal OP. The difference between the period of the OP and the set time interval on the shaper 13 should be more than the total delay of the elements 7, 8, so that the reset of the counter 3 occurred before the start of the next count. On the shaper 14 sets the code corresponding to the maximum allowable value of the sampling time. The signal "less than normal" when monitoring the memory does not make sense and cannot be implemented due to the position of switch 22 on the zero bus. When the sampling time is not more than acceptable for block 5, a signal "less" from the output of the comparison unit 12 will be received, which corresponds to the norm. If the sampling time is longer than the norm, then the signal “more” of the output of the comparison block 6 will also be sent to block 5, and the memory should be rejected. If there is no change in the information of the memory after the OP signal to the ST signal, the code comparison unit 11 will reach the “more” state. This signal through the switch 23 and the inverter 18 will prohibit the passage of the signal "more" from the output of block 12 to block 5 and will give out through the element OR 9 a signal about the end of the measurement to the input of the former 1.

 The driver 1 through the driver 6 and the delay line 7 will give a signal for the passage of signals from the elements OR 16, 17 through the elements AND 20, 21 to the block 5. However, the element And 21 will remain blocked due to the signal from the output of the inverter 18.

 Thus, if there is no change in the information, the signal “norm” will be received at the input of block 5, which corresponds to the truth when the device information matches the specified one. Then follows the signal from the output of the delay line 8, which sets the counter 3 to its initial state.

 The device is ready to receive the next OP signal.

 In practice, control of sampling time can be combined with verification of memory information. To do this, this device or several such devices can be included in the equipment for monitoring information of the memory.

 Block 5 in the simplest case can consist of three triggers (two triggers are enough to control the memory), to the inputs S of which signals “less”, “normal”, “more” are given, and the inputs R are supplied with an external reset command. Indicator devices, such as LEDs, are connected to the outputs of the triggers via keys. The control equipment for checking the memory usually has a "step" mode, in which the change of the address code and the generation of the OP signal occurs only when the "start" button is pressed. In this mode, you can check the sampling time by issuing sequentially the “reset” command to block 5 and the “start” command to the control equipment and monitoring the LEDs.

триггера установленного по сигналу "больше", а для случаев, кроме проверки ЗУ, и с

триггера, установленного по сигналу "меньше".With automatic control, it is necessary in the control equipment to send a signal from a clock generator (from it, when checking the memory, an address code and an OP signal are generated), pass through the And element, to which a signal from

trigger set on the signal "more", and for cases other than checking the memory, and

trigger set on the signal "less".

 Moreover, if the interval does not correspond to the specified one, the operation of the equipment is suspended due to the prohibition of passing the clock frequency.

Claims (1)

 DEVICE FOR PASSING TIME INTERVAL CONTROL, comprising a first input bus, an input driver, a reference signal generator, a pulse counter, a pulse counter code evaluation unit and an information processing unit, the second output of the input driver is connected to the input of a pulse former at the end of a time interval, the output of which connected through the first delay line to the input of the second delay line, characterized in that, in order to expand the functionality, elec ORs and a signal shaper along the edges of the pulse, and the pulse counter code estimator contains the first and second code shapers, the first, second, and third OR elements, the NOT element, the first, second, and third AND elements, the first and second switches, and the first and second blocks comparisons, the first inputs of which are connected respectively to the outputs of the first and second code generators, the first and second outputs of the first and second comparison blocks are connected respectively to the inputs of the first and third OR elements, and the first and second inputs are second the OR element is connected to the third outputs of the first and second comparison units, the output of the first OR element is connected to the first input of the first AND element, the output of the second OR element is connected directly to the first input of the second AND element and through the first switch to the input of the NOT element, the output of which the output of the third OR element is connected respectively to the second and first inputs of the third AND element, the outputs of the first AND element through the second switch, and the outputs of the second and third AND elements are directly connected to the first, in the second and third inputs of the information processing unit, the third inputs of the first, second and third elements And combined and connected to the output of the first delay line, the output of the second delay line is connected to the input "Reset" of the pulse counter, the outputs of which are connected to the second inputs of the first and second comparison blocks a pulse counter code evaluation unit, wherein the second input of the input driver is connected to the output of the OR element, the first input of which is connected to the output of the signal driver at the edges of the pulse, the input of which is connected to swarm input bus, and the second input of the OR element is connected to the input of the NOT element of the pulse counter code evaluation unit.