SU1679633A1 - Code auditor - Google Patents

Description

The invention relates to measuring equipment and can be used to monitor the health of digital devices. The invention provides improved device performance when monitoring a code with a unit in the high order. The device contains a decoder 1 zero, the elements OR 2 and 6, the element And 3, the element AND - NOT 4. trigger 5 and register 7. 1 Il.

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The invention relates to computing and can be used to monitor the health of digital devices.

The aim of the invention is to increase the speed of the device.

The drawing shows a functional diagram of the device.

The device contains a decoder 1 zero, the first element OR 2, the element And 3, the element AND NOT 4, the trigger 5, the second element OR 6 and the register 7. In addition, the first information inputs 8, the setup input 9 and the control input 10 of the device are shown, the first 11 and second 10 outputs of the device and the second information input 13 of the device.

Device for controlling the code "1 of p” works as follows

The code from the information inputs 8 is fed to the O-inputs of the register 7 and the inputs of the decoder 1. The decoder 1 controls the presence of units in the code and, if they are not available, forms the "Log." G 'output, which through the first input of the OR element 2 enters the device output 11 as an error signal. At the beginning of the control cycle, a pulse from the setup input 9 of the device records in the register 7 of the controlled code and resets the O-flip-flop 5 to "0".

The impulse from the control input 10 of the device provides a shift in the register 7 of the recorded code and the selection of the single state of the Ωη-output of the register 7 by the AND element - NOT 4. The OR element 6 controls the presence of "1" in the register 7 and if there are any

forms the output of the "Log.G '.

When the correct (with one unit) code is monitored, the unit state of the Ωη-output of register 7 ensures that the O-flip-flop 12 is transferred to the state "1", which goes to element 3. At the same time, the second element OR 6 controls the absence of other units in register 7 and sets at its output, the signal "Log," 0 ", thereby forming a signal about the end of control at the second output 12 of the device, the signal of the error" Log.1 "is not generated at the output of the AND element 3.

When checking the code with an error (more than one unit in the code), the first one state of the Ωπ output, read from register 7, ensures that the Ω flip-flop 5 is switched to the state "1", which goes to the element 3 to highlight the error. 6 controls the presence of a unit in the 7 bits of the controlled code remaining in the register and does not remove "Log." 1 "from its output, which also goes to another input of the And 3 element.

If the input element And 3 two "1" at its output is formed "Log.” 1 ”, which through the input element OR 2 passes to the output 11 of the device in the form of an error signal.

For example, if in the input code there is a unit in the high-order digit (Ωηexit) of register 7, then in the device the control ends in a time equal to one repetition period of Ti pulses at the control input 10 of the device.

A similar result is obtained when the error control code, for example in the presence of the first units (Ωί-output) and older (Ωη-output) discharges register 7. For the code under consideration in the control device finishes in a time equal to one periodu.sledovaniya pulse _and T control input 10 devices.

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Claims (1)

Claim Device for controlling the code "1 of p", containing a zero decoder, the output of which is connected to the first input of the first OR element, the output of which is the first output of the device, the inputs of the zero decoder are the first information inputs of the device, characterized in that in order to improve the performance of the device , an AND element, an NAND element, a trigger, a second OR element and a register, whose bit outputs are connected to the corresponding inputs of the second OR element, whose output is connected to the first input of the AND element and by the second output of the device, the output of the NAND element is connected to the C input of the trigger, the output of which is connected to the second input of the AND element, the output of which is connected to the second input of the first OR element, the first input of the NAND element is connected to the output of the ηth digit of the register , information register inputs are combined with the respective inputs of zero decoder, P-trigger input is combined with the register write is yhodom adjusting input ^- device, the second input of aND-NO element is combined with the register control input is a control input word oystva, Ω-trigger input is the second data input.