SU1674120A1 - Differentiating unit - Google Patents

Abstract

The invention relates to computing and is intended for calculating derivatives on a table of given source data when imposing additional requirements on the type of function that approximates the source data. The purpose of the invention is to expand the functionality by taking into account in the calculations of the limitations on the type of function being restored. The device contains inputs 1, group of subtractors 2, inputs 3, group of multipliers 4, inputs 5, group of multipliers 6, group of adders 7, group of registers 8, multiplexer 9, adders 10, 11, subtractors 12, 13, decoder 14, multipliers 15, 16, inputs 17, subtractor 18, adder 19, inputs 20, adders 21-24, multiplexers 25, 26, counter 27, element OR 28, counters 29, 30, blocks 31 and 32 of synchronization. 3 il.

Description

The invention relates to computing and is intended for calculating derivatives on a table of given source data when imposing additional requirements on the type of function that approximates the source data.

The purpose of the invention is to expand the functionality by taking into account in the calculations of the limitations on the type of function being restored.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the first synchronization unit; in fig. 3 is a block diagram of a second synchronization unit.

The device (Fig. 1) contains information inputs 1, a group of subtractors 2, inputs 3 sets the step, the first group of multipliers 4, inputs 5 of the first coefficient, the second group of multipliers 6. group of summators 7, group of registers 8, first multiplexer 9, first and the second adders 10 and 11, the first and second subtractors 12 and 13, the decoder 14, the first and second multipliers 15 and 16, the inputs 17 of the second coefficient, the third subtractor 18, the third adder 19, the inputs 20 of the third coefficient, the fourth - the seventh adders 21- 24, the second and third multiplexers 25 and 26, the first counter 27, lement OR 28, second and third counters were 29 and 30, first and second sync blocks 31 and 32.

The first synchronization unit (FIG. 2) contains an input 33, a trigger 34, a generator 35, an AND 36 element, a counter 37 and a decoder 38. The second synchronization unit contains a trigger 39, a generator 40, an And element 41, a counter 42, a decoder 43.

When solving a number of technical problems (for example, constructing software motions of CNC machines and robots when processing aircraft engine blades), it is necessary to solve the interpolation problem, which consists in determining the function y (x) that takes at given node points xi X2 ... xn + i are given node values fi, hfn + 1.

Good interpolation quality ensures the choice of the function of f (x) in the form of a third-degree Hermitian spline.

With this choice, the function f (x) will have a continuous derivative.

Hermitian spline f (x) with nodal points xi, X2Хп-м and nodal values fi,

f2fn-n can be set on the segment xi, xi + i in

the form

f (x) p (t) fi + (pi (t) f, -n (t) f i hi +

+ 974 (t) hifVi

pi W (1 t) 2 (1 n 2t)

pl (t) t (3 - 7t) y (t) t (1 - i} 2 p4 (T) -t2 (1- t)

(one)

hi XI-H - xi, t

x - xi hi

The values of fi, f 2. ., f n + i are chosen arbitrarily and coincide with derivatives

f (Xi), f (X2) f (xn + l).

When constructing Hermitian on spline f (x)

by the formula (1) derivatives of f 1 f 2f n + i

are parameters whose choice allows to satisfy additional requirements relating to the shape of the curve for f (x). One such requirement is convexity (e.g., when processing the surface of the blade).

Suppose that the quantities xi, .., xn + 1 and fifn + 1 form a convex system of input data. Let be

dg fl + 1-fl.

Af | -ig

where I 1n, hi XI-H - xi. It is assumed

that Afi + i Af, where i 1n-1. Geometrically, the fulfillment of these inequalities means that the piecewise linear function taking the value of yi at xi is a convex function. We describe the algorithm for choosing the speeds f i f n + i. providing the convexity of the interpolation spline f (x). This algorithm reduces to solving a system of 2 n-linear inequalities.

The function f (x) is convex if f (x) 0 for all xi x x2. However, on the segment xi, XI-M, the Hermitian spline is a third-degree polynomial. Therefore, in this segment, its second derivative f (x) is a linear function. It follows that for the convexity of the Hermitian spline f (x) it is necessary and sufficient that

f (xi + 0) 0

G (xn.1-0) 0 (2)

where i 1n.

Using representation (1), the system of inequalities (2) can be rewritten in D

2f i + fi + i ai)

fi + 2fVi ai T (3)

where ai 3Afi, I 1,., n

We will call the system of linear inequalities (3) nondegenerate if in the domain of its solutions there exists a ball of sufficiently small radius r

Let system (3) be non-degenerate and 0 I

 -t Then its solution f 1, .., fn + i can

be determined using the following algorithm. Let be

fi - a fi

Afi-i H-Af, - I - 2n (4)

f n-h a fn

the initial approximation to the solution. The derivative of the derivatives f 1,, f pi cyclically with respect to I 1,2,. , n - 1 are recalculated according to the following halts.

1 °. Calculate C - T - fVi If C: Ј ai, then go to step 2 °. If C n, then f i is reduced by (a. C) 0.4 - 21 a f c. decrease by (a C) 0 2 4 I and go to point 2 °.

2 ° Calculate С - f i f 2f ith If С ai. then go to step 3 °. If C ai, then f, increase by (a, C) -02 + 2I. a fVi increase by (a. C) 0.4 + 21 and go to point 3 °

3 °. Increment i by one If i n + 1. then the cycle of conversion of derivatives

f i f n + i ends If i n then

go to point 1 °.

The cycle of recalculation of the derivatives f i f n + 1 is repeated until

these derivatives are not stabilized, those inequalities (3) will not be fulfilled for all. If the system of linear inequalities (3) is inconsistent, then such stabilization is impossible. In this case, the algorithm finishes work when the number of repetitions of the recalculation cycle exceeds the specified value.

Differentiating device operates as follows. Before starting work, the installation in О of all the triggers and counters of the device is made (the installation chains in О of all the triggers and counters of the device are not shown). The inputs 1 are supplied with the values of the function fifn to the inputs 3 values, ..., hn 1. to inputs 5 - the number 3, and to inputs 17 - the number 0.2, to inputs 20 - the number

I When a start signal is applied to input 33, the first synchronization unit 31 starts and the trigger 34 is set to one. For the first BS 31 clock pulse in subtractors 2, the fin fi values are calculated. The second clock pulse in multipliers 4, the Afi values are calculated (A fi i D f () hi 1. no to the third - in the multipliers 6, the values ai - 3 (Af | i -i A fijhi and on the fourth - in the adders 7 the summation of the value fi (A fi - + fi + i) the first synchronization block is blocked by the signal from the fourth output of the decoder 38 and no signals appear at its outputs

On the same signal from the fourth output of the first synchronization unit, the second synchronization unit is launched. The first clock signal from its output in registers 8 records the values of fi, and the contents of counter 27 are increased by 1 On the second clock, the outputs of multiplexer 9 pass through the values of fi fVi and a, where I is the contents of the counter 27 On the third clock in blocks 10 and 11, ci1 2f i + f i-i and C21 fi 4 2f 1 + 1. and in the fourth, in blocks 12 and 13, a, - with / and ai - C2. When the values of the sign-rvs of these blocks are 10 and 11 signal 1 at the first output of the decoder, with values 00 - at the third These codes correspond to the following situations when checking inequalities (3) codes 10, 11 the first inequality does not hold (3) code 00 does not fulfill the second inequality 01 - both inequalities are satisfied

By the sync pulse at one of the outputs of the decoder And signal 1 appears. If signal 1 at the first output (the first inequality is not fulfilled), the contents of counter 27 decrease by 1. In multiplication unit 15, the value 0.2 is calculated (a, - ci) on the sixth sync pulse in block 13 - the value of 0.2 (a (ci1) - I, and on the seventh in the adders 2 1 and 22 new values of f, G, + 0.4 (a, - ci) - 21 and fVi fi + i + 0.2 (ai - ci1) - I. According to the first sync pulse, the new values of fi and f, t 1 from the outputs of the second multiplexer 25 go to the inputs of the third multiplexer 26 and are written to registers 8 through n block 32, then the cycle is repeated. If signal 1 at the second output of the decoder 14, then in blocks 16, 29. 23, 24, the values of 0.2 (a, - C21) are calculated using the corresponding clock pulses, then 0.2 (ai - C21) + I and new values of the derivatives fif i-m + + 0.2 (a, - C21) + I and f, + i fVi + 0.4 (ai - C21) + 21, When a signal appears 1, the counter 42 of the second synchronization unit is reset at the third output of the decoder 14, which results in the output of the next pulse at the first output of the block 33.

Thus, if the first inequality of system (3) is not fulfilled in the corresponding registers 8, new values of f i and fVi will be written after the first pass. When this occurs, the counter 42 overflows and the second synchronization unit will generate the next pulse at the first output, the contents of counter 27 will become equal to I. On the second pass, the first non-equality of system (3) will be guaranteed to be guaranteed, the contents of counter 27 increase again by 1 If not the second inequality of the system (3) is satisfied, then the r blocks 16, 19, 23 and 24 recalculate the new values of fi and fVi, which pass to the inputs of the corresponding registers 8. At the same time, signal 1 at the second output of the decoder 14 and the contents of counter 27 tanovits i equal to 1 on the occurrence of the third output of the decoder (performing both inequalities) system (3) resets the counter 43 and there is a transition to a new computation cycle.

The reversible counter 27 has a counting factor of n. After pairwise checking all 2n inequalities (3), the output of the overflow of counter 27 is a signal that the contents of counter 29 increase by one, the counting factor of counter 29 is equal to the maximum allowable number of passes . with n 50 number of passes does not exceed 100). If during this number of passes it is possible to ensure the fulfillment of conditions (3), then at the output of the overflow of the counter 29 a Stop signal appears, which indicates the impossibility of solving the problem. This signal clears the trigger 39

Reading the results satisfying conditions (3) from registers 8 is carried out by a counter signal 29 from the overflow output of the counter 30, having a counting factor of n. The contents of the counter 30 are increased by 1 with each occurrence of the signal at the third output of the decoder 14 and zeroed With each occurrence of a signal on the first or second outputs of the decoder 14.

Claims (1)

Invention Formula A differentiator containing a group of (n 1) -th registers (n + 1 - the number of interpolation points), the first group of multipliers and the first adder, characterized by that. what. in order to extend the functionality by taking into account the calculations of the limiters on the type of function being restored, two synchronization blocks, a group of subtractors, a group of adders, a second group of multipliers, three multiplexers, three counters, two multipliers, a decoder, an OR element, from the second on the seventh adders and three subtractors, and the 1st (I - 2, p) information input of the device is connected to the input of the readable 1st 0 group subtractor and subtractor input (i - 1) -ro group subtractor, the first and (n + 1) -th information inputs of the device are connected respectively to the input of the subtracted first group subtractor and 5 input of the calculator l-ro R. group reader, the outputs of the i-th (n -.) Subtractor of the group are connected to the inputs of the first multiplier of the 1st multiplier of the first group, the outputs of which are connected to the inputs of the first multiplier of the 1st multiplier of the second group, the outputs of which are connected to the information inputs of the i-th group of the first multiplexer, the outputs of the first group of which are connected to the inputs of the first components of the first S and the second adders whose outputs are connected to the inputs of the decremented first and second subtractors, respectively, whose inputs of the readable one are connected to the outputs of the second group of the first multiplexer. and the outputs are connected to the inputs of the first factors of the first and second (multipliers, respectively, the outputs of which are connected to the inputs of the third subtractor and the inputs of the first term 5 of the third adder, the inputs of the i-th group of the device setting (i 1 p) are connected to the inputs of the second multiplier i-ro multiplier of the first group, the outputs of the i-th (i - 2, p-1) multiplier of the first group are connected to the inputs 0 of the first term of the (i 1) -th group adder and the inputs of the second term of the i-th group adder, the outputs of which are connected to the information inputs of the i-ro group register, the outputs of the first and n-th multipliers 5 of the first group are connected to the information inputs of the first and (n-t 1) -th group registers, the outputs of the 1st group register are connected to the information outputs of the 1st device group (I - 1, item 1) and information inputs (n ( ) group of the first multiplexer, the outputs of the third group of which are connected to the inputs of the second term of the second adder, the inputs of the first coefficient of the device are connected to 5 inputs of the second multiplier multipliers of the second group, the inputs of the second coefficient of the device are connected to the inputs of the second multiplier of the first and second multipliers, the inputs of the third coefficient of the device are connected to the inputs of a decremented the third subtractor and the second term of the third adder, the first to the fourth outputs of the first synchronization block are connected to the synchronization inputs of the subtractors of the group, multipliers of the first group, multipliers of the second group and adders of the group, respectively, in addition, the fourth output is connected to the first input of the second synchronization unit, the outputs of the sign of the first and second subtractors are connected to the first and second inputs, respectively, of the decoder, the first input of which is connected to the second input of the second synchronization unit, and the second third outputs are connected to inputs of the first run and second multipliers, respectively, first and second inputs of the gate ti. respectively, and the first, m, and second inputs, respectively, of the OR elements, the output of which is connected to the ROCK of the first lock, whose information outputs are connected ;: to the control inputs of the first and third of its multiplexers, and the output overflows; with the counting input of the second counter, the overflow output of which is connected to the output of the indication of the impossibility of the device's recapture and the third input of the second synchronization unit, the first to the ninth outputs of which are connected to the synchronization inputs of the registers Rupp and counting input of the first counter, the synchronization input of the first multiplexer, the synchronization inputs of the first and second summato- ten 15 20 25 thirty 35 ditch, synchronization inputs of the first and second subtractors, synchronization input of the decoder, synchronization inputs of the third adder and subtractor. synchronization inputs from the fourth to fifth adder, the synchronization input of the second multiplexer, the synchronization input of the third multiplexer, respectively, the outputs of the third subtractor are connected to the inputs of the first components of the fourth and fifth adders, the outputs of which are connected to the information inputs of the first and second groups, respectively, of the second multiplexer, the outputs of which connected to the information inputs of the third multiplexer, the outputs of which are connected to the information inputs of the registers of the group, the outputs of the third the adder is connected to the inputs of the first sixth and seventh adders, the outputs of which are connected to the information inputs of the third and fourth groups of the second multiplexer, respectively; the inputs of the second term of the fifth and seventh adders, the output of the element OR is connected to the reset input of the third counter, the counting input of which is connected to the first output one decoder, and the overflow output is connected to the output of the sign by the result of the device Jj L /  I FIG. 2 FIG. five