SU1314336A1 - Device for calculating value of arctangent - Google Patents

Abstract

The invention relates to computing and can be used in digital computers and structures for calculating and continuously reproducing a function. The purpose of the invention is to expand the functionality by expanding the limits of change of function. The device contains a start bus 1, triggers 2, 30, blocks of elements AND 3-8, block 9 of memory constants, elements SHSh 10, 26, 28, adders 11, 14, 22, comparison circuit 12, quadrant 13, coefficient calculation block 15 , blocks 16 and 23 normalization, registers 24, 27, 29, subtractors 17, 18, 21, multipliers 19, 20, output 25, pulse generator 31, synchronization unit 32, input 33 of specifying device coefficients. 3 il. (L; and her co 05

Description

113

The invention relates to computing and can be used in digital computers and structures for calculating and reproducing the values of trigonometric inverse functions.

The purpose of the invention is to expand the scope by expanding the range of variation of the argument.

The basis of the operation of the proposed device is based on the following difference algorithm;

(one)

(i 0,1, ..., N-0

where h is the decision step; y, Wo is the initial condition, XjE GO, MOH, parameter (X .; is obtained in a certain way in the device.

Figure 1 shows the structural diagram of the proposed device; 2 is a diagram of a coefficient calculation unit; fig. 3 - the same, the rationing block.

The device contains (fig. O bus 1 Start, trigger 2, blocks of elements AND 3-8, block 9 of memory constants, block of elements OR 10, adder 11, comparison circuit 12, quadrant 13, adder 14, coefficient calculation block 15, block 16 normalization, subtracters 17-18, multipliers 19 and 20, subtractor 21, adder 22, block 23 of normalization, register 24, device output 25, block of elements OR 26, register 27, block of elements OR 28, register 29, trigger 30, generator 31 pulses, a synchronization block 32, an input 33 of setting the device coefficients.

The computation block 15 includes the following nodes: shift registers 34 and 35, trigger 36, element 37, generator 38.

The structure, blocks 16 and 23 of the normalization includes the following nodes: shift registers 39 and 40, trigger 41, element I 42, generator 43.

Block 15 for calculating the coefficient oi (Fig. 3) is used to obtain the coefficient oi from the number 1 + x incoming in the decimal code by allocating the higher bit of the number, which is easily realized on the shift registers 34 and 35 by counting the number

of the bits of the shifted number until the appearance of the most significant bit of the number being converted.

The normalization blocks 16 and 23 are the shift registers 39 and 40 that divide the values of x + 1 and h by shifting these numbers by the number of bits of the number 0.

Unit 9 of memory constants serves for storing constants and initial data:

  PPs which are located respectively on the first, second, third, fourth, fifth, sixth, seventh outputs.

The device works as follows.

Before starting work on the bus 33, block 9 receives the values x, y,,

y „, h,

2, x, triggers and registers are set to zero. Upon the arrival of the Start-up signal 1 and flip-flops 2 and 30 are set to one, and the registers 29 and 27 are entered into the initial values of y, t, y, coming from block 9, through blocks 4.28 and 5, 26, and generator 31 begins to generate a sequence of pulses entering control unit 32. The first pulse of the control unit 32, from block 9 through blocks 3 and 10 is fed to the input of the adder 11, the second pulse is the number

registered in the adder I1, where the value of x is formed, the third impulse in block 13 is performed the operation of squaring the number X, the fourth - at the output of the block

14, the number 1 + x is formed, and on the second, in block 15, a value of about is formed; by the sixth pulse, the numbers (1 +) / c6 and h / ui are formed in blocks 16 and 23, and in the seventh pulse in blocks 17 and 18 are calculated respectively values: 1 1 + x

1 + x

-V- "

2 -, on the eighth - results

obtained in blocks 17 and 18 are multiplied, respectively, by the value of y, coming from register 29 and by the value of Od coming from register 27. By the ninth pulse on the subtractor

21 a difference is formed (2- (x + 1) /

-2

/ oi) - PP (pT -) y,, and by the tenth pulse in the adder, 22, the end of the result is formed (see

31

(l), which is entered by the eleventh pulse into the register 24 and arrives at the output bus 25 and the input of the valve unit 8, by the twelfth pulse the number from the register 27 through the valve unit 7 and the unit 28 enters the register 29, and the thirteenth - the number from the output the register 24 enters through the valve block 8 and the block 26 into the register 27. By the eleventh pulse, the trigger 2 goes to the zero state and closes the valve block 3-5, thereby eliminating the use of X values at subsequent points of change:,,,, Wo.

This is the end of the first calculation cycle. In all subsequent cycles, the calculation process is defined as described, with the only difference that the increment h to the value of the current generated in the adder 11 enters at the first cycle of each cycle from block 9 through gate 6 and the OR circuit, and registers 29 and 27 through The twelfth and thirteenth cycles of each cycle are entered respectively at, ,, at ;. The process of calculating the values of the functions continues until the value of x - current becomes equal to the value of x, which are compared at the outputs of the comparison circuit 12.

At the moment of coincidence, their comparison circuit 12 switches trigger 30 to the zero state and stops the calculation process.

Thus, in the proposed device, a significant expansion of functionality is achieved, since a continuous increase in the values of the functions at a given interval is ensured.

Invention Formula

A device for calculating the arctangent, which contains a synchronization unit, six blocks of elements And, two adders, three registers, the output of the first adder is connected to the information input of the first register, characterized in that, in order to expand the scope of application by expanding the limits of the argument, the block is entered memory constants, quad, block for calculating coefficients, two blocks of valuation, two triggers, accumulate64

adder, comparison circuit, pulse generator, three subtractors, two multipliers, three blocks of OR elements, input The device start is connected to the installation inputs of the first and second triggers, the direct output of the first trigger is connected to the first inputs of the first to third blocks of AND elements , the inverse output of the first trigger is connected to the first inputs of the fourth to sixth blocks of elements And, the output of the second trigger is connected to the trigger input of the pulse generator, the output of which is connected to the clock input of the synchronization unit, the first output cat The first is connected to the second inputs of the first and fourth blocks of elements I, the inputs from the second to the fifth synchronization block are connected to the clock inputs of the third adder, the quadrator of the first adder and the coefficient calculation unit, respectively, the outputs from the sixth to the eighth

the synchronization unit is connected to the pairwise combined clock inputs of the first and second valuation units, the first and second calculators, and the first and second multipliers

telei respectively exits with de

in this case, the eleventh synchronization unit is connected to the clock inputs of the third subtractor, the second adder and the first register, respectively, the twelfth output of the synchronization unit is connected to the second input of the sixth And block, the second input of the fifth And block block, and the reset input of the first trigger

connected to the thirteenth output of the synchronization unit; the input of the device constants is connected to the information input of the constant memory unit, the first to the third outputs of which are

connected to the third entrance of the first

block of elements And, the second input of the third block of elements And, the second, the input of the second block of elements And, respectively, the fourth output

constant memory block is connected to

the third input of the fourth AND block and the first information input of the second valuation block; the fifth output of the constant memory block

connected to the input of the first term of the first adder and the input of the decremented first subtractor, the sixth and seventh outputs of the memory block 5

The tant is connected to the input of the decremented second subtractor and to the first input of the comparison circuit, respectively, the outputs of the first and fourth blocks of the And elements are connected to the first and second inputs of the first block of the OR elements, respectively, the output of which is connected to the information input of the accumulator, the output of which is connected to the second input comparison circuits with the information input of the quad, the output of which is connected to the input of the second term of the first adder, the output of which is connected to the information input of the first block The unit and coefficient calculation unit, the output of which is connected to the second information inputs of the first and second valuation units, the output of the first valuation unit is connected to the inputs of the readable first and second subtractors, the outputs of which are connected to the inputs of the first multipliers of the first and second multipliers, respectively, the outputs of which are connected to the inputs diminutable and deductible third subtractor, the output of which is connected to the input

FIG. 2

143366

the first term of the second adder, the input of the second term of which is connected to the output of the second valuation unit, the output of the first register

g is connected to the third input of the fifth block of elements AND, the output of which is connected to the first input of the second block of elements OR, the second input of which is connected to the output of the second

10 of the block of elements And, the output of the second block of elements OR is connected to the information input of the second register, the output of which is connected to the input of the second multiplier of the second

(5 multiplier and with the third input of the sixth block of the AND elements, the output of the code Topoi o is connected to the first input of the third block of the OR elements, the second input of which is connected to the output 20 of the third block of the AND elements,

the output of the third block of elements OR is connected to the information input of the third register, the output of which is connected to the input of the second factor

25 of the first multiplier, the output of the comparison circuit is connected to the reset input of the second flip-flop, the output of the first register is the output of the device.

41)

/

ofig.

20 and 21 I

-W

42

With t. P.

Claims (1)

Claim A device for calculating the arc tangent, containing a synchronization block, six blocks of AND elements, two adders, three registers, the output of the first adder is connected to the information input of the first register, characterized in that, in order to expand the scope by expanding the limits of the argument, they are introduced constant memory block, quadrator, coefficient calculation block, two normalization blocks, two triggers, accumulating adder, comparison circuit, pulse generator, three subtractors, two multipliers, three blocks of elements OR, input The start of the device is connected to the inputs of the installation of the first and second triggers, the direct output of the first trigger is connected to the first inputs from the first to third blocks of elements AND, the inverse output of the first 10 trigger is connected to the first inputs from the fourth to sixth blocks of elements And, the output of the second the trigger is connected to the trigger input of the pulse generator, the output of which is connected to the clock input of the synchronization block, the first output of which is connected to the second inputs of the first and fourth blocks of AND elements, outputs from the second to fifth block and syn20 synchronization is connected to the clock inputs of the third adder, the quadrator of the first adder and the coefficient calculation unit, respectively, the outputs from the sixth to the eighth 75 synchronization blocks are connected to pairwise combined clock inputs of the first and second rationing units, first and second subtractors, first and second multipliers, respectively; outputs from the ninth to eleventh synchronization blocks are connected to the clock inputs of the third subtractor, second adder, and first register, respectively, twelfth the output of the synchronization unit is connected to the second input of the sixth block of AND elements, the second input of the fifth block of AND elements and the reset input of the first trigger 40 are connected to the thirteenth output of the synchronization block, the input of setting the device constants is connected to the information input of the constant memory block, the first to third outputs of which 45 are connected to the third input of the first block of AND elements, the second input of the third block of AND elements, the second input of the second block of AND elements, respectively fourth exit 50 constant memory block is connected to the third input of the fourth block of AND elements and the first information input of the second normalization block, the fifth output of the constant memory block 55 is connected to the input of the first term of the first adder and the input of the decreasing first subtracter, the sixth and seventh outputs of the memory block are connected to the input of the decreasing second subtractor and to the first input of the comparison circuit, respectively, the outputs of the first and fourth blocks of elements And are connected to the first and second inputs the first block of OR elements, respectively, whose output is connected to the information input of the accumulating adder, the output of which is connected to the second input of the comparison circuit and to the information input square ora, the output of which is connected to the input of the second term of the first adder, the output of which is connected to the information input of the first rationing unit and the coefficient calculation unit, the output of which is connected to the second information inputs of the first and second rationing units, the output of the first rationing unit is connected to the inputs of the subtracted first and second subtractors whose outputs are connected to the inputs of the first factors of the first and second multipliers, respectively, whose outputs are connected to the inputs of the decremented one and subtract of the third subtractor, whose output is connected to the input 1314336 6 of the first term of the second adder, the input of the second term which is connected to the output of the second normalization block, the output of the first register 5 is connected to the third input of the fifth block of AND elements, the output of which is connected to the first input of the second block of OR elements, the second input of which is connected to the output of the second 10 block of AND elements, the output of the second block of OR elements is connected to the information input of the second register, the output of which is connected to the input of the second factor of the second 15 multiplier and to the third input of the sixth block of elements whose output is connected to the first input of the third block of OR elements, the second input of which is connected to the outputs 20 of the third block of AND elements, the output of the third block of OR elements is connected to the information input of the third register, the output of which is connected to the input of the second factor 25 of the first multiplier, the output of the comparison circuit connected to the reset input of the second trigger, the output of the first register is the output of the device. FIG. 2 Fig. 3