SU1651283A1 - Device for solving integral equation of measurement converter of flow velocity - Google Patents

Abstract

The invention relates to computing and is intended for use as a specialized computing device. The purpose of the invention is to increase accuracy and speed. The device contains a register 1, block Shnsh-6 | 2 divisions, register 3, block 4 divisions, a group of elements NOT 5, a combination adder 6, a multiplier 7, an analog-digital converter 8, an element OR 9, an element AND 10, a registrar 11, a group of elements AND 12, an element NOT 13, a group elements AND 14, register 15, multiplier 16, group of elements NOT 17, functional converter 18, multiplier 19, register 20, accumulative adder 21, unit 22 of comparison, group of elements NOT 23, register 24, block 25 of comparison, group of elements And 26 - 28, the multiplier. 29, a group of elements HE 30, a functional converter 31, a multiplier 32, a group of elements OR 33, a group of elements HE 34, a group of elements AND 35. a division unit 36, a group of elements HE 37, a combination adder 38, a group of elements AND 39 - 41, a multiplier 42, a functional converter 43, a group of elements OR 44, a multiplier 45, a cumulative adder 46, a multiplier 47, a combination adder 48, a division block 49 and a synchronization block 62. 2 Il. Ml TY-I Ј About sla 00 OJ s) s aittrast (ft about /

Description

The invention relates to computing and is intended for use as a specialized computing device.

The purpose of the invention is to increase accuracy and speed.

Figure 1 shows the structural diagram of the proposed device; figure 2 - timing diagram of the device.

The device consists of the first register 1, the first division unit 2, the second register 3, the second division unit, the first group of elements NOT 5, the first combination adder 6, the first multiplier 7, the analog-digital converter (ADC) 8, the element OR 9, the element AND 10, the third register 11, the first group of elements And 12, the element NOT 13, the second group of elements And 14, the fourth register 15, the second multiplier 16, the second group of elements NOT 17, the first functional converter 18, the third multiplier 19. the fifth register 20, first accumulative sum ator 21, first comparison unit 22, third element group NO 23, sixth register 24, second comparison unit 25, third one - fifth group of elements 26 and 28. fourth multiplier 29, fourth group of elements 30, 30 second functional converter 31, n that multiplier 32, the first group of elements OR 33, the fifth group of elements is NOT 34, the sixth group of elements is And 35, the third block 36 is divided, the sixth group of elements is HE 37, the second combiner adder 38. the seventh is the ninth group of elements And 39-41, the sixth multiplier 41, the third functional converter 43, the second group of elements OR 44, the seventh multiplier 45, the second cumulative adder 46, the eighth multiplier 47, the third combinational adder 48, the fourth dividing unit 49, the clock generator 50, pulse counter 51 and the decoder 52, synchronization inputs (buses) 53 - 61 and block 62 sync.

The basic equation of a flow velocity transducer is a differential equation of the first kind,

, l «| U + r0u (t) - C0V2 (t) (1)

with the initial condition w (0) o) 0, where I is the moment of inertia of the flow of the anemometer;

w (t) is the speed of rotation of the rotor; go is the coefficient of viscous friction; Constant, depending on the parameter of the anemometer;

V (t) is the flow rate.

five

,

0, „

The construction of specialized computing devices for solving equation (1) in many practical cases does not justify itself, since the variable w (t) included in equation (1) is of experimental origin, which leads to large errors in the resulting solution in numerical implementation. Therefore, it is highly advisable to reduce equation (1) to an equivalent integral equation. Such an approach to solving the differential equation (1) not only allows for numerical implementation to reduce the error of the resulting solution, but also reduces the number of computational operations.

The integral equation equivalent to the differential equation (1) has the form

J K (t-S) V (S) dS DG) (t), (2) o

where K (t-S) - - (tab -) t-BT (s) TO i

core integral equation.

Equation (2) is a Volterra integral equation of the first kind. Using the property, the capacity section of the kernel allows you to represent equation (2) as

 / in V (S) dS w (l) (3)

about

The device implements a modified algorithm for the numerical implementation of the integral equation (1) by the quadrature sum method using the formula of average rectangles with a constant discretization step h const no calculated expression

(, l °} r ° o

-K-) those

where,. (r) l,., h (, - rs are discretization nodes.

In the device, the main computational operations are performed in parallel.

The device begins to function with the arrival of a start pulse on the generator 50 pulses. A decoder 52 sequentially extracts pulses at one of its outputs cyclically with a module defined by a scaling factor of counter 51.

Consider the 1st cycle of the device. Before the start of operation, the values of the coefficients I, th and Co are recorded in the first 1 / second 3 and third 11 registers, respectively, and the step values h and the integration limit T are in registers 20 and 24. Register 15, accumulative adders, functional converters, division blocks and the multiplications are set to the zero state. In the first clock cycle, the ADC 8 is triggered by the control signal of the bus 53 of the decoder, to the input of which the control signal of the bus 53 enters through the elements. Both 10 and OR 9, while the second input of the element AND 10 receives a signal from the first output of the first comparison unit 22. It should be noted that the element And 10 is open only when h 0, i.e. at the beginning of the calculation. On the same signal from the bus 53, blocks 2.4,21 and 15 are triggered, at the outputs of which at the end of the first cycle, respectively, -p, ti are set.

h iO, 5p.

In the second clock cycle, the multipliers 7,16,29,42 and ADC 8 are triggered by the control signal from the bus 54 of the decoder. The group of elements I 12 is open only in the first cycle, i.e. at h 0. At the same time, the values are respectively set at the outputs of the multipliers.

K (,

i4

i

The value of + is formed at output I

the second combiner adder 38. At the end of the second clock cycle, at the output of the ADC 8, the value (tk (h) is generated; the control signal is received through the OR 9 element).

In the third cycle, according to the control signal from the bus 55 of the decoder in the first 18, second 31 and third 43 functional converters, the values of the functions are formed respectively

-Jjrash

Gh-jjslt

 I7

e and e -1 i

In the fourth clock cycle, the multipliers 19 and 32 are triggered according to the control signal from the bus 56 of the decoder;

, 5С0х Г0

em (

(o) -ЈL).

In the fifth clock cycle, according to the control signal from the bus 57 of the decoder, the division block 36 is activated. Element group 26 is open

only in the first cycle (at ti h), in the remaining cases it is closed, and the group of elements And 27 is open only at ti h. The group of elements And 14 is closed only when ti h, a in the remaining cases it is open. The control signal in this cycle in block 36 forms the value

4W / - (,

if ti h, and (Do (ti)) / h, if tl h. In the sixth cycle, according to the control signal of the bus 58 of the decoder, the multiplier 45 is triggered. At that, the group of elements AND 39 is open, if tj h, the group of elements And 41 is open, if ti h, otherwise it is closed. At the end of this cycle, the output of the multiplier 45 is given the value

(eb

if ti h, and V (m), if tl - h. In the seventh cycle, the second cumulative adder 46 is triggered by the control signal of the bus 59 of the decoder. At the output of which the sum

-a Ze

.v (ti4M.

In the eighth cycle, a multiplier 47 is triggered according to the control signal of the bus 60, the output of which at the end of this cycle is the value

W. -r i fn z x -p e z j + i v /, v V ° a r0) e e 0Vlti4b

In the ninth cycle, the control unit 61 of the decoder triggers the division block 49. At the same time, the group of elements AND 40 is open if ti h, and in other cases it is closed. At the output of block 49 receive the value of the flow rate at the i-th step

(s.1 and d 3: 2e 1h () 4t) i} p,

-la. (.

Which through a group of elements 39 is fed to the input of the second group of elements OR 44, the outputs of which are the output of the device. The second input of the group of elements OR 44 is supplied with the value from the output of the group of elements AND 41.

Comparison unit 22 serves to control the And 10, 12, elements (4, 27, 28, 26, 39 - 41, Comparison unit 25 - to establish the moment of the end of calculations or the stop of the device.

The time diagram (Fig. 2) illustrates the operation of the device, the degree of parallelization of the computational process, as well as the reduction of time spent on preparatory work related to the calculation of the values ah (0), оъ (п) and V (h /, 2),

Claims (1)

Claims — A device for solving an integral Comparison of a flow rate measuring transducer comprising first and second registers, a first cumulative adder, a first multiplier, a first combinational adder, a first group of elements, a synchronization unit, the outputs of the first combinational adder are connected to the inputs of the first multiplier of the first multiplier , with the fact that, in order to increase accuracy and speed, the second through eighth multipliers, four division blocks, element nt OR, AND element, two groups of OR elements, second and third combinational adders, second cumulative adder, three functional converters, two comparison blocks, analog-to-digital converter, third to sixth registers, nine groups of AND elements, second to sixth groups of elements are NOT and the element is NOT, the outputs of the first register are connected to the inputs of the divider of the first division unit, the outputs of which are connected to the inputs of the second multiplier of the first multiplier and the first multiplier of the second multiplier, the outputs of the second register a is connected to the inputs of the divisible first division block and the inputs of the divider of the second division block whose inputs are connected to the outputs of the third register, and the outputs are connected to the inputs of the NOT elements of the first group whose outputs are connected to the inputs of the first term of the first combination adder which are connected to the outputs of elements AND of the first group, the information input of the device is connected to the information input of the analog-digital converter, the outputs of which are connected by the first inputs of the And the first, second groups, the outputs of the fourth register are connected to the inputs of the second multiplier of the second multiplier, the outputs of which are NOT connected to the information input of the first functional converter through the second group of elements, to 15 20 25 thirty 35 40 45 50 55 the outputs of which are connected to the inputs of the first multiplier of the third multiplier, the inputs of the second multiplier of which are connected to the outputs of the first multiplier, and the outputs are connected to the first inputs of the AND elements of the third group, the outputs of which are connected to the first inputs of the OR elements of the first group, the outputs of which are connected to the inputs of the third block divider division, the inputs of the dividend which is connected to the outputs of the elements of the second group, the outputs of the fifth register are connected to the information inputs of the fourth register, the first inputs of the elements in the fourth group by the inputs of the first group of the first comparison unit and the information inputs of the first cumulative adder, the outputs of which are connected to the inputs of the first term of the second combinational adder, the inputs of the second group of the first comparison unit and the inputs of the first group of the second comparison unit, the inputs of the second group of which are connected to the outputs of the sixth register, and the output is connected to the device Stop output, the first output of the first comparison block is connected to the second inputs of the AND elements of the first group, the first input And through the element NOT with the second inputs of the AND elements of the second group, the output of the element AND is connected to the first input of the element OR whose output is connected to the start input of the analog-digital converter, the outputs of the first division block are connected to the inputs of the first multiplier of the fourth multiplier, the inputs of the second multiplier which are connected to the outputs of the first cumulative adder, and the outputs through the elements of the NOT fourth group are connected to the information inputs of the second functional converter, the outputs of which are connected to moves the first factor of the fifth multiplier, the inputs of the second multipliers are connected to the outputs of the first multiplier, outputs of the third group elements are not connected to the first inputs of AND gates of the fifth group, the second output of the first comparator unit is coupled to second inputs; the elements of the fourth and fifth groups, the outputs of the elements and the fourth group are connected to the second inputs of the elements OR of the first group, the outputs of the fourth register through the fifth group of elements are NOT connected to the first inputs of the elements AND the sixth group, the outputs of which are connected to the inputs of the second term of the second combinational adder , the outputs of the fifth register through the elements of the NOT sixth group are connected to the inputs of the third 9 the second combinational adder, the outputs of which are connected to the inputs of the first multiplier of the sixth multiplier, the inputs of the second multiplier of which are connected to the outputs of the first division unit, and the outputs are connected to the information inputs of the third functional converter, the outputs of which are connected to the inputs of the first coi the multiplier of the seventh multiplier, the outputs of which are connected to the information inputs of the second accumulator, the outputs of which are connected to the inputs of the first multiplier of the eighth multiplier, the inputs of the second multiplier of which are connected to the outputs of the fifth multiplier, and the outputs of the first multiplier of the third combiner with the inputs of the divisible fourth division block, the outputs of which are connected to the second inputs of the elements of the And sixth group and the first inputs of the elements And the seventh groups, the outputs of which are connected to the first inputs ele1651283 ten five 0 five OR of the second group, the outputs of which are connected to the outputs of the device and the inputs of the second multiplier of the seventh multiplier, the second output of the first comparison unit is connected to the second inputs of the AND elements of the seventh group and the first inputs of the AND elements of the eighth group whose outputs are connected to the inputs of the second addend the third combinational adder, the outputs of the third division block are connected to the second inputs of elements And the eighth group and the first inputs of elements And the ninth group, the outputs of which are connected to the second inputs element in the OR of the second group, the third output of the first comparison unit is connected to the second inputs of the third and ninth elements of the group, the outputs of the elements of the fifth group are connected to the inputs of the divider of the fourth division block, the outputs of the synchronization block connecting to the synchronization inputs of the fourth register, accumulative adders, multipliers , functional converters and dividing units, as well as the second inputs of the AND element and the OR element.