SU1413626A1 - Device for computing function of two arguments - Google Patents

Abstract

The invention relates to computing and allows the class of tasks to be extended to be expanded by calculating functions not represented as a product of the functions of the first and second arguments. The device contains the registers of the first 1 and second 2 arguments, the synchronization block 3, the memory block 4, in which the logarithms of the modules are stored and the signs of the approximation coefficients multiplexers 5 and 3, the memory block 6, in which the logarithms of the increments of the first and second arguments are stored, buffer registers 7 and 11, adders 9 and 10, memory unit 12, which performs potentiation with base two, a combination shifter 13, a controlled inverter 14 and an accumulator 15, form the result of the calculations. 1 z.p, f-ly, 3 pcs. (L with

Description

FZHZ

00 O) tsd

but

. iii, f

The invention relates to computing technology, is intended for calculating the functions of two variables and can be used in digital fast digital specialized computing devices of information-measuring systems of control systems.

The purpose of the invention is the extension of the JQ class of solvable tasks by calculating functions that are not represented in a combination of functions of the first and second arguments,

The figure shows the j5 functional scheme of the proposed device; FIGS. 2 and 3 are the functional schemes of the combination shifter and the synchronization unit, respectively

The device contains registers of the first 1 and second 2 arguments, synchronization block 3, first memory block 4, multiplexer 5, second memory block 6, first buffer register 7, multiplexer 8, first and second adders 9 and 25 10, second buffer register 11, third memory block 12, combinational shifter 13, controlled by inverter 14, accumulator 15o. Combination shifter 13 (Fig. 2) contains a permanent memory block 16, a group of multiplexers 17 and a register 18, Block 3 synchronization (FIG. 3) consists of a pulse generator 19 and a binary hexadecimal Meters withstand 20 "

The device calculates the values of the function at a given point (x, y) by piecewise quadratic approximation of the original function by the polynomial

35

F (x, y) ao, i + a / 5 x + a,. - l j; Lu + + a. and JJ- X doo, (1)

de 5 + / 3 X, + d y, X}, Y;)

0.1 1.1 S | i

the initial 45 point of the approximation area;

coefficients of the approximating polynomial, depending on the function to be approximated and the initial point (xj, v.), in the vicinity

Q

five

0 5 d

five

0

five

0

which approximation is made.

The values of the coefficients A .. a j are determined either by the least squares method from the condition of minimizing the sum of the squares of the errors, or from the conditions of minimizing the maximum error. Codes x. , lx, and J 4U are formed, respectively, by the highest and lowest bits of the arguments.

To exclude multiplication operations, the conversion (1) is converted to

RoeYd) F (x, y) - sign (ag i) 2 + sign

(a ,;), o. .sign (a ,,).

. , , C47 (5, l)

+ sign (ajp2 +

.sign (a.V), /. (V,) 4,

.signCa ,,) .-. J (2)

The logarithms of the coefficient modules and the signs of the coefficients are stored in the first block of 4 memory, the logarithms of x, and the charger in the second 6 "Argument codes are entered in registers 1 and 2.

The device works as follows.

When entering the first and second arguments in registers 1 and 2, the entry gate arriving at the input after the device start-up closes the accumulating adder 15, register 11 and the counter 20 of the synchronization unit 3

Simultaneously with the arguments supplied to the device inputs or somewhat earlier, the code of the calculated function is set at the input of the device function setting. From memory block 4, the logarithm of the module of the zero coefficient is read as an integer part with a sign and a positive fractional part and is sent to the input of the first term of the adder 10, to the input of the second term of which register 11 is supplied the zero code, the fractional part of the value of the logarithm of the module of the zero coefficient enters memory block 12, from which the antilog of the fractional part is traced by the information input to the combination shifter 13. If you need to put a part of the logarithm.

correct and different from zero, the anti-log code shifts on the group of multiplexers 17 to the left by a number of positions equal to the whole part of the logarithm, if negative, the shift is done to the right

In order to reduce the number of multiplexers 17 in the group, the shift is performed in two steps during the positive half-clock of the sync signal arriving at the highest bit of the address input of the .16 fixed memory unit, the minor part of the generated number is output to the outputs of the multiplexers 17, register 18 and from the outputs of this register enters the output of the shifter 13 (low-order bits); during the negative half-cycle, the higher part passes through the output of the multiplexers, supplied directly to the output of the shifter 13. Thus, the zero-factor code given to the fixed-commanding form, pass the controlled inverter 14, or is inverted if the sign of the coefficient coming from the second output of memory unit 4 They are either equal to one (the coefficient is negative), or remain unchanged with a zero sign. Since the accumulating adder 15 was reset to zero at the moment of entering the arguments, the zero coefficient is simply written to the internal register of the accumulating adder 13 with a positive edge of the sync signal received at its gate input.

In parallel with the transformations of the zero coefficient, multiplexer 5 passes to the address output of the block, 6 memories, the code of the lower part of the first argument, from memory 6 is read the logarithm of the base two lower parts of the argument and this value is fed to the input of the second term of the adder 9 and the information the input of the buffer register. 7 To the input of the first term of the adder 9 multiplexer 8 supplies the code zero. The lower part of the first argument logarithm passes through the adder 9 with a positive edge of the clock signal, entered mp 11 "

The same positive edge of the sync signal increases the counter code 20 by one, which leads to a change in the address of memory block 4 and the control code of multiplexers 5 and 8,

ten

15

20

15

30 35

40 45 50,

55 From the first output of memory block 4, the code of the logarithm of the module of the first coefficient is read and in the adder 10 is added to the logarithm of the lower part of the first argument received from register 11, and the fractional part is always positive, and the whole can be both positive and negative.

The logarithm of the fractional part is potentiated in memory block 12, shifted by the combination shifter 13 and summed up in the accumulating adder 15, taking into account the sign J received on the control input of the inverter 14, with a value of zero coefficient.

At this same time, multiplexer 5 passes the lower part of the first argument to output, and multiplexer 8, the code from register code 7, and the output of adder 9 produces the doubled logarithm code of the lower part of the first argument, which corresponds to the logarithm of the square of this number. The resulting value is recorded in register 11 and in the following cycle it is summed with the log-; rhyme of the second coefficient. Thus, the process is repeated, with the only difference that at each new clock cycle clock from memory block 4, the logarithm of the module of the next coefficient is read, multiplexer 5 on the third and fourth clock skips the code of the lower part of the second argument, on the fifth and sixth the lower part of the first argument, the multiplexer 8 skips the zero code on the third cycle, and on the fourth, fifth and sixth - the code from the register 7 output. After passing six clock cycles in the accumulating adder 15, the value of the calculated function is generated, and -, in the high-boundary code discharge counter 20 will prohibit job generator 19 imt- pulses that regard as a sign of the result is ready.

Thus, the introduction of new blocks and links allows one to implement a piecewise quadratic approximation algorithm acceptable to the set. smooth functions of two variables, which includes a narrower subset of functions with separable arguments, and, thus, solve the problem of expanding the class of computed functions.

pm lla

and

gaining

Claims (2)

1. A device for calculating the functions of two arguments, containing registers of the first and second arguments, two multiplexers, two buffer registers, three memory blocks, the first adder, accumulating adder, combinational shifter, synchronization unit, information inputs of the registers of the first and second arguments The inputs of the first and second arguments of the device, respectively, the P-code of the upper bits of the register of the first argument are connected to the first address input of the first memory block, the output of the first buffer register It is connected to the first information input of the first multiplexer, the output of which is connected to the input of the first term of the first adder, whose output is connected to the information input of the second buffer register, the output of the third memory block is connected to the information input of the combinational shifter, the output of the accumulating adder is the output result of the device, the first output of the synchronization block is connected to the second address input of the first memory block and the control inputs of the first and second multiplexers, the second output block SinScheonization is connected to the synchronization inputs of the first and second buffer registers, the combinational shifter and accumulating adder. In order to expand the class of solved problems by calculating functions not represented as a product of the functions of the first and second arguments, the second adder and controlled inverter, the information input and output of which are connected to the output of the combinational shift 0 five 0 5 p five 0 five and informaton input of accumulating adder, respectively, the output of the higher bits of the second register register is connected to the third address input of the first memory block, the first output of which is connected to the input of the first term of the second adder, the second input of which is connected to the output of the second buffer register, outputs the fractional and integer parts of the result of the second adder are connected to the address input of the third memory block and the control input of the shift value of the combinational shifter, respectively, the second output The first memory block is connected to the control input of the controlled inverter and to the transfer input of the accumulating adder. The low-order bits of the first and second argument registers are connected to the first and second information inputs of the second multiplexer, the output of which is connected to the address input of the second memory block. whose output is connected to the information -, input of the first buffer register and the input of the second term of the first adder, the second information input of the first multiplexer is connected to the input of the logic L device start input of which is connected to the inputs of write registers of the first and second-arguments and reset inputs of the synchronization unit, the second buffer register and the accumulator, the output characteristic completion cyclin sia sync block is output indication unit is ready result 2. The device in accordance with claim 1, 1 and 2, so that in order to increase the number of calculated functions, the fourth address input of the first memory block is the input of the function setting of the device. FIG. 2