SU1671047A1 - Dynamical shift register - Google Patents

Abstract

The invention relates to automation and computing and can be used to store and shift information. The purpose of the invention is to expand the scope of the register due to the possibility of performing a reverse shift. The register contains memory elements divided into three groups, a second write transistor and a second reset control transistor are additionally introduced into each memory element. 2 Il.

Description

The invention relates to automation and computer science and can be used to store and shift information.

The aim of the invention is to expand the scope of the register due to the possibility of performing a reverse shift.

FIG. 1 shows the basic electrical circuit of the register; in fig. 2 - time diagrams of stresses when shifting to the right and left.

The register contains 1,2,3 memory elements, respectively, having clock inputs 4,5,6 and connected to the zero potential bus 7. Each memory element (EF) consists of a MIS varactor 8, a key transistor 9, the first 10 and the second 11 write transistors, the first 12 and second 13 transistor control reset, reset transistor 14, preset transistor 15

and a preset control transistor 16. Each EA has an input 17 and an output 18. In FIG. 1 also shows the left 19 and right 20 serial inputs of the register, the left 21 and the right 22 recording outputs, the left 23 and the right 24 inputs of the register reset.

FIG. 2 shows the following voltages: U4, U5, U6 - at the clock inputs 4.5, - at the input 18 of the 1st EP, i 1.4; U15 - on the gate of the transistor 15 of the 1st EP; U14; - on the gate of the transistor 14 i-ro ES; U10; - at the output of the 1st EP.

The description of the operation of the device is given on the example of four series-connected EPs (Fig. 1). If, prior to the arrival of the control voltage, the clock input 4, connected to the first ES, at the input 17, corresponds to the logical O (in Fig. 2, this situation at the moment tg-t7 at the input of the first ES), in this ES, the key

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the transistor 9 and the transistor control preset 16 are closed, since their gates are connected to the input 17, and the control voltage supplied to the corresponding control input does not pass to the preset transistor 15 and to the output 10 of this EA, and to adjacent ESs through the first 10 and the second 11 write transistors, which are opened by the control voltage (time t7-t8), will write the voltage of the logic O (to the inputs 17).

If, prior to the arrival of the control voltage, the clock input connected to the second EA (moment) at input 17 corresponds to logic 1, then the key transistor 9 and the control transistor of preset 20 are open and the control voltage goes to the gate , preset 15 (Ш52), opening it and connecting the gate of the J4 reset transistor to the bus 7, i.e. closing it 25 (U14,). At the same time, the clock voltage through the open transistor 9 arrives at the output of the second EA as logical 1, and through the first ED 10 and second 11 transistors opened by this voltage, write this logical 1 into the next (third EA) and previous first EP at the same time. It should be noted that the property of MDP-variators is used here - an increase in capacitance in the presence of potential at its gate (in our case connected to input 17). Therefore, the clock voltage increases the voltage at input 17 above logic / M. Thus, the key transistor 9 at the moment operates in a steep region, this eliminates the loss of amplitude of the pulses at the outputs 13 due to the threshold voltages of the transistors 9, and the variation of the threshold voltages in this case does not reflect on the variation of the amplitudes of the output pulses. Upon termination of the clock voltage (t) C, the inputs of the second ED and its neighboring ES remain recorded voltages of logical 1, the preset transistor through the open transistor of the preset control 16 (shutter connected to input 17) closes with the end of the pulse at the clock input but the discharge transistor of discharge 14 remains closed because

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If at the time tc-tg the clock voltage is fed to the input connected to the third EM (shear in the forward direction), then, similarly to the work of the EA described above, the output of the third EA produces a pulse, which coincides with the clock voltage the pulse through the reset control transistor 12 of the second EA will record and the gate of the reset transistor logical 1, this reset transistor will open and connect the output 18 of the third EA with the bus 7, thus ensuring good noise immunity of the device. In addition, at this moment (ty-tg), transistors of the recording of the third EP of logical 1 will be written into the neighboring EP.

Thus, at the end of the clock voltage at time t, logical 1 is recorded at the inputs 17 of the second EC and its neighboring EPs. Depending on the further sequence of receipt of the clock voltages at inputs 4.5 and b, the shift 1 continues along the register in the forward or the opposite direction.

Claims (1)

Invention Formula A dynamic shift register containing memory elements, each of which consists of a MOS-varactor, a key transistor, a first write transistor, a reset transistor, a first reset control transistor, a preset transistor, and a preset control transistor, with the 11DP-varator gate connected to the key transistor gate , the drain and source of the MISVaractor the source of the key transistor is connected to the gate of the first transistor of the record, the source of the key transistor, the drain of the first transistor of the record and the drain of the transistor reset are combined and are the corresponding parallel register output, the source of the first transistor of the recording of each memory element, except the last one, is connected to the gate of the key transistor of the subsequent memory element, the source of the first transistor of the recording of the last memory element is the right register write output, transistors of the first and last memory elements the registers are corresponding to the left and right serial inputs of the register, the sources of the reset and preset transistors are connected to the register bullet potential bus, the gate of the reset transistor is connected to the drains of the preset transistor n of the first transistor of the reset control, the gate and source of the first transistor of the reset of each memory element, except of the latter, is connected to the drain of the reset transistor of the subsequent memory element, the gate and the source of the first transistor controlling the reset of the last memory element and is the right output of a register reset, characterized in that, in order to expand the field of application of the register due to the possibility of reversing the shift, the drains of the MDP-va generators (3i-2) -x, (3i-1) -x and 3i- The x memory elements 1 Ј i Ј n, n are the number of register bits, are the first, second, and third register inputs, respectively, and the second transistors are entered into each memory element. 0 five Recording and resetting control signals, the gate, drain and source of the preset control transistor are connected respectively to the gate of the key Transistor, the MOS-Varactor drain and the gate of the preset transistor, the gate and drain of the second transistor of the recording transistor are connected to the gate and drain of the first transistor of the recording transistor, and the source the second transistor recording each memory element, except the first, is connected to the gate of the key transistor of the previous memory element 5, the source of the second transistor recording the first memory element Is the left output of the register entry, the drain of the second transistor of the reset control is connected to the drain of the preset transistor, and the gate and source of the second transistor of the reset control of each memory element except the first one is connected to the drain of the previous transistor of the previous element, and the gate and source of the reset control transistor. the first memory element is the left register reset input. 0 20 I (pue.f FIG. g