SU1410103A1 - Sequential asynchronous register - Google Patents

Abstract

The invention relates to automation and computing and can be used in the construction of asynchronous devices for receiving and transmitting information. The aim of the invention is to simplify the register. To achieve this goal, each register memory cell, consisting of two OR-NOT elements and two inverters, contains two key elements, each of which is made on a MOS transistor, the source, drain and gate of which are connected respectively to the second and third inputs and output of the corresponding element OR - NOT. The number of MOS transistors that make up the register's memory cell is reduced from 18 to 14 as compared to the prototype. The frequency of receiving (or issuing) information is 1/6 I (CL is the switching delay of the MOS transistor). 1 il.

Description

The invention relates to automation and computing and can be used in the construction of asynchronous devices for receiving and transmitting information.

The aim of the invention is to simplify the register.

The drawing shows the scheme proposed) pei-Istra.

The register on MOSFETs contains memory cells 1, each of which consists of two symmetric chains 2, made on inverter 3 and the OR element - ME 4, the first 5 and second 6 inputs of the chains and the first 7 and BTopoii 8 outputs of the chains , a control input 9 of the register readout, an ipfortmentary outputs 10 of the register, a control output 11 of the register entry, information inputs 12 of the register, an OR-NOT 13 element, a first and second inverter 14, a third iverter 15 and k; 1 switch element 16, made on MIS-trapsistor.

The register works as follows.

The cell state l.i (value in the inverse information output 7 of each chain) corresponds to 10 — 0 is written in the cell, 01 is recorded in the cell 1; 00 - no information in the cell. The state I1 in the course of the register operation in the cell does not arise due to the cross connection between the chains of the cell.

The sets of fluxes and inputs 12 correspond to: 01 - the source transmits 0; 10 - source transmits 1; 00 - the source does not transfer information to the register. Set 11 is prohibited.

The value on the input of register 9 corresponds to: 1 - the receiver is ready to receive information from the register; O - receiver irin l from the register ipfor.matsiyu.

Information is recorded in cell l.i on inputs o and 6 when the cell l. (I-1) records information, and in cell l. (I + l) the information is erased or has a value opposite to that being written. The ipformation step in the cell l.i occurs only when the same information is recorded in the cell l (i + l), and in the cell l. (I-1) the information is erased or has the opposite value to the underestimated cell l, i.

Let there be no information in the initial state in the register, i.e. values on the inverse and forward information inputs of memory cells 00 and 11, respectively. Let also unit 1 be fixed at input 9. The source sends information to the register, setting at its inputs 12, for example, set 01. As soon as this information is located in the first cell, the output of the register 11 will be 0. Appearance 1 on the inverse m. the information output of the cell opens the key element 16 of the corresponding chain; as a result, the control and information inputs of the chain are short-circuited among themselves. It means.

that while the control input of this chain (the inverse information output of the corresponding chain of the next cell) and the value is O, the register does not react to the change, however, changing the value at the control input is impossible if there is an O on the information input. Now the source can set the value of the input 12 to 00 in order to then transmit a new piece of information. After that, the information is rewritten from the first register cell to the second one, allowing clearing of information in the cer- tain cell. As soon as the first cell of the register information is erased, the source can write the following normal information to the register, at the same time there will be a census of information from the second to the third cell.

Thus, the sequential transfer to the register of chunks of information at a fixed value at its input 9 continues until the entire register is filled. With this, the 1 between the two cells, storing adjacent pieces of information with the same values, will be

5, one cell in which information is erased, if the value of adjacent pieces of information is different, then they are stored in adjacent cells.

Let set 00 be fixed at inputs 12 of the register, and as a result of filling the register with information, the state of its last cell is 10. After receiving this information from outputs 10 of the register, the receiver sets 9 O at its input, which causes erasure of information in the last cell. As a result, if in nosolne and penultimate 5

five

the register cells contain portions of information with different values, the possibility of rewriting information from the penultimate cell to the last one appears, then the information is not being copied from the cell,

0 preceding the last but one, etc. As soon as the information in the last cell is erased, the receiver can turn on 9 of register 1, i.e. prepare for receiving the next one. a piece of information. Thus, the successive reception of information from the pei-ister with a fixed dial-up at its inputs 12 continues until the entire register is cleared, i.e. no information will be erased in all its cells. With the simultaneous operation of the source and

Q .1 Information about the process of transmitting it proceeds in a manner similar to that of information.

The recording time (erase) of information in the cell of the asynchronous register is 2, - the delay of the MOS transistor. The frequency of the shift operation in the register is

1 / bch:

The number of MOSFETs constituting the memory cell of the proposed register.

compared with the prototype reduced from 18 to 14.

Claims (1)

Asynchronous serial register on MOS transistors containing memory cells, each of which consists of two symmetric chains of an OR-NOT element and an inverter, whose input is connected to the output of an OR-NOT element of this chain and the first input of an OR-NOT element the chain of the given memory cell, the second input of the OR-NOT element of each chain of each memory cell, except the last one, is connected to the output of the OR-NOT element of the corresponding chain of the next memory cell, and the third input of the OR-NOT element of each chain whose and a memory except the first connected to the output of inverter chain corresponding previous memory cell, wherein the inverter outputs the last 0 five memory cells are information outputs of the register, characterized in that, in order to simplify the register, key elements are inserted into each chain of each memory cell, each of which is made on an L DP transistor, the drain, the source and the gate of which are connected respectively to the second and the third inputs and output of the OR-NOT element of the given youth, three inverters, the inputs of the first and second inverters are the information inputs of the register, and the outputs are connected to the third inputs of the OR-NOT elements of the first memory cell, the input of the third inverter is the control input of the register reading, and the output is connected to the second inputs of the OR-NOT elements of the last memory cell, and the element. OR is NOT, the inputs of which are connected to the outputs of the elements OR of the first memory cell and the output is the control output of the register record. /-BUT-// /-WITH A /}