SU1261130A1 - Reception code-interval device - Google Patents

Abstract

The invention relates to telecommunications. The speed increases with an increase in the length of code combinations. The device contains an input matching unit I, a control unit 2, a counter 3, a buffer register 4, r-clock clock pulses 5, a polarity decoder 6, reshivy block 7, a code comparison comparison block 8, a distributor (P) 9, a switch 10 , drive (H) And, shift register (PC) 12, and element And 13. Reception of information is carried out until H is received and recorded through ko fyatatop 10 in H And all signs of the waveform, while dah PC 12, db recorded I. Then the element And 13 generates a signal that resets PC 12 and P 9 to its original state and resolves into. “. 1 reading information for execution. T, arr. To the front of the side, a signal is sent. The goal is achieved by introducing P 9, switch 10, N P, PC 12 and zimenta And J3. I class g (L f co

Description

And the acquisition relates to telecommunications can be used in information transmission systems.

The purpose of the invention is to improve speed by increasing the range of code points.

The drawing shows a structural electrically a diagram of the proposed device.

The receiving nitral-code device contains the input matching block I, Olok 2 control, counter 3, the buffer register 4, the 5-clock pulse generator, the decoder 6 polarity rashakshchy flea 7, the flea 8 comparing running hombiations, the distributor 9, the hommutator 10, the drive II, register 12 shift, elements And 13.

The device works as follows.

When the first parcel arrives, the input flea matching I issues to the polarity decoder 6 a signal about the polarity of the received parcel, which is memorized and prohibits the passage of other signals from the input matching unit 1, the crocg signal of the arrival of the last parcel. On a signal of arrival of the first parcel, a polar polar desnfriuur 6 starts a 5 clock pulse and issues a signal to control unit 2, which is delayed by one time otcht of the generator 5 clock pulses and arrives at its counting input.

When a second parcel arrives, input flea matching I issues to fleas 2 controls the polarity signal of the parcel, which remembers, prohibits the arrival of the third parcel signal of the same polarity to read information from the outputs of binary counter 3, opens the outputs of binary counter 3 and the inputs of the buffer register 4 and prepares a circuit for issuing a control signal for opening the inputs of the buffer register 4 and turning on the code comparison unit 8. If the second parcel arrives of positive polarity, then the block with 2 controls opens the pr - “chains. Odes of binary counter 3, and if negative, then inverse, while the combination of moves is recorded in the m-) bits of the buffer register 4.

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When the third parcel arrives, the input matching unit 1 issues a polarity signal to the control unit 2, which, if the third polarity is opposite to the second, is remembered, arrives at the opening of the binary counter 3 entrance and prohibits the passage of any other parcels, including false, to open the information outputs of the binary counter 3. If the dressing is positive, 10 open the direct outputs of the binary counter 3, and if negative, then the inverse ones, and the code combination is fed to the input of the comparison unit 8 marketing combinations.

In addition, on the third parcel signal, control unit 2 opens informational T-1 outputs of buffer register A and a signal arrives to turn on block 8 for comparison of code combinations. If the code combinations from the outputs of the binary counter 3 and the buffer register 4 are equal to one another, the comparison code block 8 outputs the signal to the decisive block 7, which is stored by its first stage.

When the fourth parcel arrives, the input matching unit 1 generates a signal about the polarity of the parcel, Koropi .i enters the decoder 6 polarity. If the polarity of the fourth premise is opposite to the first one and it arrived simultaneously with the overflow pulse of binary counter 3, then the polarity decoder 6 writes to the high bit of the buffer register A 1, if the first premise was positive and the last negative, then. and outputs a signal to solving unit 7. In this case, solving unit 7 produces a signal that opens the information inputs of switch 10 and records the first bit of shift register 12, which is prepared for recording with a decisive signal from the first output of distributor 9. In addition At the same time, the first w switch keys of the switch 10 are opened with the same signal, through which information from the output of the buffer register 4 is stored in the first m memory elements of the storage device 11.

The overflow pulse of the binary counter 3 enters the control-control unit 2, where it is delayed by the time required for recording information in

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drive 11. The delayed signal resets the memory of the control unit 2, the polar decoder 6, the reset block 7, the buffer register to the real-time counter 3, and also enters the input of the distributor 9, the signal from which goes to the input of register 12 shift and opens the second years. the keys of the switch 10, the reception cycle of the second and subsequent digits repeats the reception cycle of the first one. In this case, the distributor 9 makes m sequential switching, connecting the next inputs of the accumulator Ii through the switch 10 to the outputs of the buffer register 4, and the shift register 12 counts the correctly received characters. Receipt of information is carried out as long as all the signs of the code are received and written to the drive P, while all bits of the shift register 12 must be written I. Then element I I3 outputs the drive M to read the drive - information on the actuator, resets the shift register I2 and the distributor 9 to the initial state of the long side of the perRL Tit Sngnll Knit.Chnin

Claims (1)

Invention Formula A slot-code device containing an input matching unit, the first and the third part of which is connected to the BbW and the second inputs of the control unit respectively, and the first and second inputs of the polarity decoder, the first output of which is connected to the first - the 40th input of the decision block, the second input of which is connected to the first output of the counter, to the third input of the decoder of polarity and to the third input of the control; the fourth 45 input of which is connected to the second output of the decoder of polarity and to the input Compiled by O. Geller. Editor M. Nedolu, c. 5247/59 Circulation 624 Subscription, BffHUHH USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 . four clock generator, a single output of which is connected to the fifth input of the control unit, the first output of which is connected to a quarter input of the polarity decoder, the third output of which is connected to the first input of the first register 1, the second j input of which is connected to the second output of the control unit The third output of which is connected to the first input of the counter, the second outputs of which are connected to the third inputs of the buffer register and to the first inputs of the code combination comparison unit, the second inputs of which are connected to the first output m of the buffer register, whereby the output of the block of code combinations is connected to the third input of the decisive block, characterized in that, in order to improve performance by increasing the length of the code combinations, the shift register, the AND element, the switch, the accumulator and the distributor, the outputs are entered into it which are connected to the first inputs of the co-switch and to the first inputs of the shift register, the outputs of which are connected to the inputs of the element I, the output of which is connected to the first input of the storage device, to the second input of the register of the spoiler and to the first input The clerk, whose second trip is connected to the fourth output BL1) of the v-board, to the fifth input of the polarity decoder, to the second input of the counter, to the fourth input of the buffer register and to the fourth input ;; 7 is a decision block, and its code is connected to the third input the shift register and the BTopbw input of the switch, the outputs of which are connected to the second inputs of the drive, the first and second outputs of the buffer register are connected respectively to the third and fourth inputs of the switch, and the inverse output reH jpaTopa of clock pulses is connected to control unit input.