SU1624370A1 - Device for functional checking large integrated circuit - Google Patents

Abstract

The invention relates to a measuring and control technology and can be used to control digital integrated circuits. The purpose of the invention is to expand the field of application due to the possibility of controlling other types of microchip kits and increasing the reliability of coyrol by increasing the information content of the control - achieved by introducing a register 17 of type of work, clock control unit 18, control trigger 19, digital comparator 20, address counter 21, elements 22 and 23 delays, block 24 elements OR. The device also contains a microprogram control unit 1, an action and reaction setting unit 2, a pulse generator 3, a synchronization unit 4, a time delay generator 5, a waveform generator unit 6, a level driver unit 7, switches 8 and 9, a comparator unit 10, block 11 comparison, error memory block 12, delay element 13, counter 14 cycles, output and input buses 15 and 16. Block 18 of the control of clock pulses contains a converter of 25 levels, trigger 26, elements I. 1 Cpf-ly, 2 il . SO with

Description

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Claims (2)

Claim 1. A device for the functional control of large integrated circuits, containing a microprogram control unit, a unit for setting actions and reactions, a pulse generator, a synchronization unit, a time delay shaper, a signal shaping unit. shaper block! '' levels, two switches, block, comparators, comparison block, error memory block, delay element, counter, input and output buses, and the group of the first outputs of the microprogram control block is connected to the groups of the first inputs of the block for setting actions and reactions. Generator-mountain ^!, pulses, synchronization unit, time delay shaper and signal shape former block, first g · ,, '/ od block.? impacts tasks and reactions is connected to a first input mikrepoogrammnogo control and input of the shutdown ^g ene? raterz imgulsov, whose output is connected to second inputs of impacts reference block and reactions node synchronization and shaper delay time, the group of second outputs impacts reference block and reactions connected with the group second vdddor of the block of formers of the form sig · -.-g-s, whose departures through the last ice: e1.lte · '.! but the connected block of shaper-quenchers and the first switch are connected about the output bus of the device, the input bus is connected in series through the second switch and the ko / lpar block; delays, the group of nerves ^v g · departures of the comparison unit is connected to the group of the first ENTRANCE; block·. AMYATI SSHIOOK. EXIT * Dykotorsgo connected! ¹ with a group of second inputs of the firmware control unit. the third input of the militia unit is connected to the first outpost of the time delay shaper, the outputs of the synchronization unit are connected to the group of third inputs of the unit of the form of the helium receiver οιπηολοβ. distinguishing e s; l> m. Thats ·, with the workshop extension of the volume. '. ayui prima' blue and increasing the dos dos OS = AND 'OHipO / Hi. g, device / entered. ,, job register, sync control blog, t o, ν g cp control, digital comparator, address counter, two additional delay elements (second and third;) and Ryt?,: elements OR. gn'.i al.; · ”by Oy Shed flask assignments to the rival ¹¹ - · th pe a c, · ;! it is ideally connected to the group of highs- '1 .-. od, s of the error memory block, and π νас rpei -, .- χ: outputs 11 with the group of the third inputs of the error memory block and with the inputs of the first delay element, the group of fourth inputs of the block the error memory is connected to the outputs of the address counter, and the group of fifth inputs is connected to the group of second outputs of the microprogram control unit, the group of third outputs of which is connected to the inputs of the work register, the group of first outputs of which is connected to the group of first inputs of the clock control unit, the second input of which it is single with the output of the OR block, the inputs of which are connected to the group of second outputs of the comparison unit, the third input of the clock control unit is connected to the output of the control trigger, the fourth input is with the output of the second delay element, and the output is with the sixth input of the error memory block and the output of the address counter , the first input of the control trigger 20 is connected to the input of the third delay element, the second input to the output of the digital comparator, the group of the first inputs of which is connected to the group of the second outputs of the register of type of work, the second 25 outputs d shaper time delay counter is connected to inputs and second and third delay elements and the outputs of the counter are connected to a second group of inputs to the numerical comparator inputs and a group of seventh error memory block. 2. The device according to claim 1, wherein the sync pulse control unit 5 is itself executed on a level converter, a trigger, and seven logical elements And, the inputs of the level converters form the group of the first inputs of the sync control unit, the first input 10 trigger forms the second input, and the first and second inputs of the first element And form the third and fourth inputs of the clock control unit, respectively, the first, second and third outputs of the level converter 15 are separately connected to the first inputs of the second, the third and fourth elements And, the second inputs of which are connected to the fourth output of the level converter, and the outputs are separately connected to the first inputs of the fifth, sixth and seventh elements And, respectively, the second inputs of which are connected to the output of the first element And, and the outputs are combined and form the output of the control unit clock, the third input of the sixth element And is connected to the first input of the trigger, the second input of which is connected to the output of the fourth and second input of the seventh element And, and the output to the third input of the seventh element AND. FIG. 2