SU1621028A1 - Multichannel microprogram control device - Google Patents

Abstract

The invention relates to computing, can be used in the design of computer systems with a programmable architecture. It provides a reduction in the capacity of the microcommand containing n microprogram control channels. Each of the modules contains a block of 2 memories (shpopropism). register of 5 commands, register 3 of HSPOBPI, multipexor 4 forces of the forcing of the address and register of 8 microinstructions, Stump dos 1pgl, tsp due to the entry into the device of the p-phase generator 1, and in each channel - the key 7 with the three-stable Synchronization of the 1st firmware control (i 1 s,., n) with the i-phase 1 generator and the combination of the outputs of the keys 7 provide a conflict-free separation of the general unit 2 pgm tch (firmware) by all channels of the program management, which allows single instance identical micr programs of channels about 2 or about. us yy

Description

The invention relates to computing and can be used in the design of computing systems, in which the possibility of programmatic tuning is incorporated, and modifying the structures that are most adequate to the problems to be solved.

The purpose of the invention is to reduce the memory capacity of micro-instructions.

Fig. 1 shows a diagram of a multi-channel firmware control device; Fig 2 shows a view of the clock pulses generated by the n-phase clock pulse generator.

The device consists of a p-phase generator 1 of clock pulses, block 2 of memory (microprogram), in which microprograms are executed, executed by each channel of microprogram control, and includes n microprogram control channels k ,,, kt ,. Each channel contains a register of 3 conditions, a multiplexer of 4 conditions, a register of 5 commands, an address generator 6 (microcommand) that can be implemented, for example, on the basis of a K1804VU4 chip, a key

7 with three stable output and register

8 microcommand

Consider the operation of a multi-channel firmware control device, having previously made common observations for all channels of firmware control

Triggered registers 3 and 8, as well as the driver 6 Occurs on the positive edge of the clock pulse. The outputs of the switches 7 are turned off at a single voltage at the output resolutions. When a negative impulse arrives at the resolution input, the output of the key 7 is derived from the third state. In this case, the information from the input of the key 7 is fed to its output. Register 3 records the values of conditions coming from both the outputs of various operating units and from other sources. The selection of the condition arriving at the corresponding input of the imaging unit 6 is ensured by supplying information from the corresponding output of the register 8 to the control input of the multiplexer 4. The logic of the operation of the imaging unit 6 is determined by the information at its input of the address control. On the first and third information inputs of the dyurmi0

five

0

five

0

five

0

five

0

five

The rotator 6 can be transitions to the address from register 8 or to the command code from register 5, respectively. A command code is written to register 5 when an external tracking signal arrives at its clock input. The use of micro-command register 8 provides microprojects for pipelining in each channel of microprogram control. The micro-command execution peak starts with the arrival of a positive front of the clock, along which the next micro-command is entered into register 8. The current micro-command execution is combined with a sample of the next, including two consecutive time phases: calculation the next address and the micro-command sample itself from memory block 2 (firmware) about

It is assumed that the operation of the firmware control channels k1f kg, ... k is synchronized respectively by synchrophases 1, FZ (),), which are depicted in FIG. 2.

Let us begin the description of the operation of the multi-channel firmware control unit from some intermediate time point t. At this time point, in the nth firmware control channel, the next microcommand is loaded into register 8, and the output of key 7 goes into the third state. At the same time, the output of the key 7 of the first channel is turned on. Therefore, the address of the next microcommand of the first channel from the output of the imaging unit 6 is fed through the key 7 to the input of the microprogram memory block 2. Thus, in the time interval tQ- t, the next microcommand is read in the first channel, and in the remaining channels the addresses of the following microcommand are formed. At time t, the read microcommand is entered into the first channel register 8, the output of the key 7 of this channel is disconnected from the input of block 2, and the output of the key 7 of the second channel is turned on. Consequently, in the time interval t, | - 12. extracting the next microcommand from block 2 in the second channel are combined and forming the addresses of the following microcommands in the other channels. At the time t2, the selected microcommand is written to the second channel register 8, the output

51

the key 7 of this channel is transferred to the third state, and the output of the key 7 of the third channel is turned on. Thus, all the firmware control channels will work until tiro inclusively. In the time interval Ts, the micro-commands of the n-th channel are read from block 2 and the micro-addresses of the other channels are generated. . Beginning with the time interval t N, the operation of the channels is repeated as described in p.

Claims (1)

Invention Formula A multi-channel firmware control device containing a memory block and n firmware control channels, the k-rt channel (k 1, p) containing the condition register, the instruction register, the condition multiplexer, the address driver and the micro-command register, the outputs of the walking address, the address driver, analysis of conditions and micro-operations are connected respectively to the first information input of the address generator, the control input of the address generator, the control input of the condition multiplexer and the k-th output of the device, the second and the third information inputs of the address driver are connected respectively to the outputs of the condition multiplexer and pe86 the command hub, the information input and the synchronization input of which are, respectively, the k-th input of the command and control of the device command, the k-th input of which logical conditions are connected to the information input of the condition register, the output of which is connected to the information input of the conditions multiplexer, in order to reduce the memory capacity of micro-commands, the device contains a p-faecal clock pulse generator, and each channel additionally contains a key with a three-stable output, with the information input key and with the three-stable output of the k-ro channel of the microprogram control, is connected to the output of the kiru address of the k-ro channel of the microprogram control, the outputs of the key with the three-stable output are interconnected and connected to the address input of the memory unit, the output of which is connected to the information inputs of micro-command registers of all microprogram control channels, the k-th output of the n-phase clock generator is connected to the synchronization inputs of the condition register, address generator, micro-command register and the control input of the key with a three-stable output of the k-ro microprogram control channel . F1 Fg