SU1606642A1 - Electric combination lock - Google Patents

Abstract

The invention relates to a technique for protecting various objects from unauthorized access, in particular, to code locks and allows to increase the secrecy of the device. In the code setting unit 3, the lock reference code is stored, and in the code setting unit 15, the display element number of the display 13, from which the true user reads the signs for opening the lock, is stored. The generator 6 and the frequency divider 8 determine the frequency of changing the address in the counter 10. In accordance with the address from the fixed memory unit 11, characters are read and written into the unit 12 of registers. At the same time, they are displayed on the board 13, and one of them, in accordance with the code stored in block 15, enters through the switch 14 for comparison in block 4 of the comparison. The other input of block 4 receives the characters of the reference code from the output of block 3. To activate the execution unit 5, it is necessary to press the switch of the control unit 1 at the moments of indication on a certain display element of the board 13 of the required characters. After dialing the next character in the counter 10, a random code is generated. 3 hp f-ly, 5 ill.

Description

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The invention relates to a technique for protecting various objects from unauthorized access, namely to combination locks.

The aim of the invention is to increase

secrecy.

FIG. 1 shows a block diagram of the device; in fig. 2-5 are respectively functional diagrams of the control unit, the pulse distributor, the comparison unit, the switch.

The device (Fig. 1) contains a control unit 1, a pulse distributor 2, a code setting unit 3, a comparison unit, an execution unit, 5 pulse generator 6, element 7 AND, frequency divider 8, element 9 OR, counter 10, unit 11 constant memory, block 17 of registers, board 13, switch 14, additional block 13 installation code.

The control unit 1 is designed to record the moments of comparison of the code signs coming from the switch output with the reference code signs, to form a random number in the counter 10, and also to set the device to its initial state. The control unit 1 can be executed according to the scheme shown in FIG. 2. It contains a switch 16, a contact chattering circuit 17, delay elements 18 and 19, one-shot (pulse shapers on a leading edge) 20 and 21, a switch 22 (intended for resetting the device).

The distributor 2 pulses is designed to generate control signals. It can be performed according to the scheme shown in FIG. 3. The distributor 2 pulses contains a counter 23 and a decoder 24 and a delay element 25.

The code setting unit 3 is for setting the reference code. It may contain, for example, memory elements.

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The register unit 12 is designed to receive a random memory readable from the unit 11 of a chaotic sequence of characters and display it on the display 13. Unit 12 contains shift registers, the number of which is equal to the number of binary bits used to encode characters (when using decimal digits, the block 12 contains four registers). The width of the registers n determines the number of characters stored at each time point in block 12, and is chosen such (for example) so that the possibility of storing the characters when they are displayed on the board 13 is excluded.

Comparison unit 4 is designed to compare the reference code with the dialing code. It can be performed according to the scheme illustrated in FIG. 4. Comparison unit 4 contains comparison unit 26, element 27 And, counter 28.

The execution unit 5 is designed to open the lock bolt. It may contain an electromagnet connected to the output of the NAND element, while the inputs

The NAND element is the input of block 4. The NAND element output is the collector of a power transistor.

The pulse generator 6 is designed to provide a cyclical code change in the counter 10. The frequency of the generator 6 is chosen high, for example, MHz. Element I 7 is designed to enable the arrival of pulses from generator 6 to the counting input of counter 10 by a signal from the output of control unit 1, thereby allowing the random code to be written to the account number 10. Frequency divider 8 is designed to form pulses with a period of the order of one second that ensures reliable user input of the required characters.

The counter 10 is designed to count the number of pulses from the output of the element OR 9 and thereby to form the address of the character read from the fixed memory unit 11.

The fixed memory unit 11 is intended for the sequential storage of various permutations (P ,,, N) of the characters used. The number (N) of permutations stored in the block 11 of the permanent memory must be large enough

on the order of a few thousand hours, so that when reading the characters from block 11 in succession, it seems that they are random. When using decimal characters, the sequence of characters read from AND may be:

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Table 13 is designed to display the contents of the block 12 registers. The number of familiarity scoreboard 13 is equal to the number stored in the block. 12 character registers, i.e. register size.

0 The switch 14 is intended to issue in the comparison unit 4 one of the characters currently stored in the register 12, the output number is determined by a code received from the output of the additional code setting unit 15.

5 It can be performed, for example, according to the scheme shown in FIG. 5. Switch 5 contains elements AND 29.1.1-29.m.n. and elements OR 30.1-ЗО.т., where m -

the number of registers, n is the size of registers.

The additional code setting unit 15 is designed to store the code defining the number of the display element of the board 13, only when indicating the required code sign (output from the output of the register unit 12), is it possible to compare it positively with the corresponding sign of the reference code, since at the same time this sign is issued to the input of the comparison unit. Block 15 can be performed, for example, on microswitches.

The device works as follows.

When the power is turned on by the signal to the input of the distributor 2 pulses, the device is set to the initial (closed) state.

The generator 6 produces high-frequency pulses, which are fed to the input of the splitter 8 frequency. From the output of the frequency divider 8, low frequency pulses flow through the element 9 OR to the counter 10, in which addresses are sequentially generated, at which characters are read from the permanent memory 11. The next character read by the signal from the output of element 9 OR is recorded in the block 12 of registers, while in block 12 the previously recorded characters are advanced and one of them is pushed out. On the board 13, a new state of the block 12 of registers is indicated.

At the same time, one of the characters from the output of register block 12, the number of which is determined by the code received from the output of code setting block 15, is output via switch 14 to the input of block 4 of comparison. When the pushbutton switch of the control unit 1 is pressed, a signal is set at the output of the signal received at the input of the distributor 2 pulses, according to which the output of the code setting unit 3 is the sign of the reference code, which is applied to the comparison unit 4. Then, the pulse coming from the output of block 1 to the comparison block 4 compares the sign from the output of switch 14 with the sign of the reference code. If the characters are equal (i.e.) if the switch of the control unit 1 was pressed at the moment of displaying the required sign, on the display element whose number corresponds to the code installed on the additional code setting unit 15), a unit is added to the counter of the comparison unit 4. After that, the signal from the output of the control unit 1 is allowed to pass the high-frequency pulses through the elements AND 7, OR 9 to the counter 10, and the triggers of the frequency divider 8 are reset. At the end of the action

Bc: -nala at the input of the element And 7 at the output of the counter 10, a random code is set and the operation of the frequency divider 8 is permitted. Further, the process repeats.

After a set of all characters from the output of the distributor 2 pulses to the input of the Executive unit 5 receives the enabling signal. If all signs are dialed correctly, then the output of the comparison unit 4 is also received by the enabling signal, the execution unit 5 is triggered. Then after a certain time interval, a signal from the output of the distributor 2 at the output of the comparison unit 4 is set

5, the signal arriving at the execution unit 5. From the output of the distributor 2 pulses, the inhibit signal also arrives at the input of the execution unit 5, and the execution unit 5 is turned off. In the device selected as a prototype, the set of required characters is carried out by pressing the control unit switch at the moments of their indication on the scoreboard, providing a display of only one character. Therefore, in the prototype

5 it is possible to compromise the reference code by visually reading it from the scoreboard at the time it is typed.

In the proposed device, a large number of characters are displayed simultaneously (for example,

0 a few dozen tkov). The set of required characters is carried out at the moments of their indication on one specific indicator from the entire set of indicators that constitute the scoreboard, and the number of this indicator is given by a code stored in tay5 not from unauthorized persons. In addition, the signs displayed on the scoreboard are a chaotic sequence that partially changes with a frequency of about 1 Hz by advancing it by one.

Q sign. After the next character is typed, a complete change of the displayed sequence occurs.

An example of a set of code is shown in the table for code 15 (the required indicator 5 is conventionally shown in the form of a square).

Thus, during the dialing of the reference code, it is not possible to determine its value from the entire set of randomly displayed characters to an outside observer, which determines the increased secrecy of the device.

Claims (4)

Invention Formula I. Electron-code lock containing a control unit, an output connected to the first input of the pulse distributor, the first output connected to the executive unit, a generator, the output of which is connected to the first input of the AND elements and the frequency divider, the outputs of which are connected to the inputs of the OR element, the output of the connected to the input of the counter, the code setting unit, the switch, the first group of inputs of which is connected to the outputs of the first code setting unit, the comparison unit, the first inputs of which are connected to the switch outputs, in The second input is to the second output of the control unit, the third input is to the second output of the pulse distributor, the board, characterized in that, in order to increase secrecy, a permanent memory block, a register block, an additional code setting block are inserted, and the counter outputs connected to the inputs of a fixed memory block, outputs connected to the inputs of a register block whose outputs are connected to the second inputs of the switch and to the display, the second input of the register block is connected to the output of the OR element, and the third output of the control unit It is connected to the second inputs of the AND element and the frequency divider, the first output of the comparison unit is connected to the second input of the execution unit, the second outputs of the comparison unit are connected to the inputs of the additional code setting unit, the outputs connected to the second inputs of the pulse distributor. 2. A lock according to claim 1, characterized in that the control unit comprises first and second switches, a chattering circuit, first and second one-shot, first and second delay elements, and the outputs of the first switch are five 0 five 0 The cut of the deblocking circuit is connected to the first one-oscillator, the output of which is the first output of the control unit and connected to the first delay element, the output of which is the second output of the control unit and connected to the input of the second delay element, the output connected to the second one-oscillator the third output of the control unit, and the output of the second switch is connected to the input of the first delay element. 3. The lock according to claim 1, characterized in that the pulse distributor comprises a counter, a decoder, a delay element, the inputs of the counter and the decoder being the second input of the pulse distributor, the first output of the decoder is the second output of the pulse distributor, and the second output of the decoder is the first output of the pulse distributor and connected to the delay element, the output connected to the R input of the counter, whose C input is the first input of the pulse distributor. 4. The lock according to claim 1, characterized in that the switch contains AND elements and OR elements, the first inputs of the AND elements are the second inputs of the switch, and the n-inputs of the AND elements are the first inputs of the switch, and the outputs of the AND elements are connected to the inputs of the OR elements, whose m outputs are switch outputs. KblockZKb /) K6 / iOKLi5 From block FIG. 2 Fig-5 Q.5 Revealed 0/776 / 1.2 FIG. FIG. five