RU1791809C - Device for entry of information - Google Patents

Abstract

Usage: keyboard input devices, Essence; the device comprises a counter 1, a read-only memory unit 2, a matrix of switching elements 3, a delay element 4, an AND element 5. 1 ill.

Description

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The invention relates to automation and computer technology and can be used in keyboard input devices.

Known devices for inputting information containing a matrix of switching elements, a switch, a decoder, a counter, logic elements,

A disadvantage of the known devices is their low reliability.

Closest to the technical essence of the claimed invention is an information input device comprising a first counter, a decoder, a matrix of switching elements, a switch, a delay element, a first trigger, an AND element, a second trigger, and a second counter associated with inputs with the output of the first counter and the switch, and the output with one of the inputs of the first trigger, the second input of the And element connected to the output of the switch, and the clock inputs of the second trigger and the first counter to the clock input of the device,

A disadvantage of the known device is the low reliability of operation, due to significant hardware costs for its implementation.

The aim of the invention is to increase the reliability of the device.

The goal is achieved in that a memory block is inserted into a device containing a matrix of switching elements, a counter, a delay element, an AND element, and a device sync input is connected to the counter input and the delay element input, the outputs of the counter are connected to the corresponding inputs of the memory block Thus, the outputs of the memory block are connected to the inputs of the matrix of switching elements, and the outputs of the matrix of switching are connected to the corresponding inputs of the memory block, the output of the delay element and one of the outputs of the memory block are connected to the input of the AND element, the output of the element And it is an information output to the devices of the corpse of outputs of the memory unit — the address outputs of the device.

. The drawing shows the proposed device.

The device comprises a counter 1, a memory unit 2, a matrix 3 of switching elements, a delay element 4, an AND 5 element.

The memory unit 2 can be implemented on a read-only memory device, for example 573RF2.5; 556RT6.7, etc.

The device operates as follows.

Computer clock pulses are sent to the device sync input. These pulses are fed to the input of counter 1 and lead to

sequentially changing the states of the outputs of the latter, which in turn provides a change in the states of the outputs of the memory unit 2 associated with the inputs of the matrix 3 of switching elements. Information from the outputs of the matrix 3 of switching elements is fed to the corresponding inputs of the memory unit 2, moreover, if the interrogated key of the matrix 3 is commutation; press the elements, then at the information output of the memory unit 2 there is a signal that through the element And 5 is fed to the output of the device, the delay element 4 provides the delay required to complete the transients in the counter 1 and memory unit 2, as well as bounce Matrix keys 3 switching elements.

A computer reads information from the information output of the device during the action of a clock pulse with a delay equal to or greater than the delay generated by the delay element 4.

The address of the pressed key of the matrix 3 of switching elements is read from the address outputs of the memory unit 2. The memory unit 2 is a read only memory,

Thus, the introduction of a memory unit and new communications into the device allows eliminating a decoder, a switch, two triggers and a second counter, thereby reducing the cost of implementing the device and, therefore, increasing the reliability of its operation.

Economic efficiency from the use of the proposed device in comparison with the prototype is achieved by reducing hardware costs and increasing the reliability of its operation.

Claims (1)

The claims A device for inputting information comprising a matrix of switching elements, a counter, a read-only memory unit, wherein the outputs of the counter are connected to the inputs of the first group of the read-only memory unit, the outputs of the first group of which are connected to the horizontal buses of the matrix of switching elements, the counter input is a device sync input moreover, in order to increase the reliability of the device, an element And, a delay element, vertical buses of the matrix of switching elements are connected to the inputs of the second group memory cards, the outputs of the second group of which are information outputs of the device, the input of the counter is connected to the input of the delay element, the output of which is connected to the first input 517918096 element And, the second input of which is connected to the element And is the readiness output with the output of the read-only memory block, the output of the device.