SU1601771A1 - Device for receiving self-clocking pulse sequences - Google Patents

Abstract

The invention relates to telecommunications and can be used in information transmission systems employing self-synchronizing time-interval codes. The aim of the invention is to improve noise immunity. The amplitude quantizer 1, when the signal exceeds a threshold level, generates amplitude-normalized pulses that are converted by a converter 2 into a series of pulses, the number of which is proportional to the time that the input signal exceeds the threshold level. The output signal from the converter 2 through the delay unit 9 is fed to the decoder 6, performing one-step decoding of the received pulse sequence, which is output to the device. When receiving each code combination, the received number of pulses is reproduced, which is subtracted from the readings of the reversible counter 15. The binary code of the latter continuously monitors the average frequency of interference pulses at the information input of the delay block 9. The binary code from the outputs of the reversible counter 15 arrives at the output of the device. ". Reversible counter 16 generates a code corresponding to the ratio of the frequency at the input of the delay unit 10 to the frequency at its clock input. The code of the reversible counter 16 is fed to the code-voltage converter 8, the signal from which adjusts the threshold of the amplitude quantizer 1 in accordance with the actual signal-to-noise ratio. 1 il.

Description

The invention relates to the field of electricity and can be used in information transmission systems that use self-synchronizing time interval.

The aim of the invention is to increase omehowa steadfast news.

On. The drawing shows a structural electrical circuit of the device for receiving aero-synchronizing pulsed sands. Q

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The device contains an amplitude quantizer 1, a converter 2, a needle duration — the number of pulses, a generator of 3 such pulses, a divider 4 frequencies, a distributor of 5 pulses, a decoder 6, a generation of 15 OR 7 series of pulses, a code-voltage converter 8, a delay block 9, additional delay unit 10, first AND second 12 and third 13 synchronizers, additional synchronizer 14, reversible counter 15, additional reversible counter 16, first 17 and second 18 elements OR, additional element PI 19, element II 20, D- trigger 21.

A device for receiving self-synchronizing pulse sequences 25 operates as follows.

 a self-synchronizing pulse sequence, mixed with interference pulses (input signal) is fed to the input of the amplitude quantizer 1, in the initial state in which the 30 SRI is set the threshold level corresponding to the specified signal-to-noise ratio. This is done by setting the signal at the signal input signal-to-noise ratio of a device for receiving self-synchronization of rudimentary pulse sequences, the corresponding code, and writing it into an additional reversible counter 16 on a signal at the input of the recording resolution of the device for receiving self-synchronizing pulse sequences. The code of the reversible counter 16 is fed to an additional converter 8, the code-voltage, where it is converted into a voltage and fed to the control input of the amplitude quantizer 1. / ir- The actual signal-to-noise ratio of the test 45 is based on a continuous evaluation of the ratio of the average frequency information pulses to the average frequency of the pulse interference Amplitude quantizer 1, when the signal exceeds the threshold level, generates pulses normalized in amplitude and having different duration depending on the time Sheni interference threshold level, and via the inverter 2 are converted into a series of pulses. The number of pulses in these series is directly proportional to the time the input signal exceeds the threshold level, and the duration of the pulses is equal to the duration of the information pulses. Pulsed after 2 ohs, you are determined de de ling for poo by yes nor s m s

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the sequence from the output of converter 2 is simultaneously fed to the information input of the delay block 9 and through the first synchronizer 11 to the summing input of the reversible counter 15. From the data outputs of the delay block 9, signals arrive at the corresponding inputs of the decoder 6, which performs one-shot decoding of the received pulse by sequence. The information received by the decoder b is fed to the output of the device for receiving self-synchronizing pulse sequences. The pulse sequence from the additional output of the delay unit 9 through the third synchronizer 13 and the second element OR 18 is fed to the subtracting input of the reversible counter 15. At the initial time, the mixture of information and interfering pulses is fed only to the summing input of the reversible counter 15 and the counting of these pulses begins. After the delay time, the same pulse sequence arrives at the subtractive input of the reversible counter 15, which from this moment begins to add and subtract the same number of pulses. Thus, after the delay of the operation of the device for receiving self-synchronizing pulse sequences, the contents of the reversible counter 15 cease to change at a constant average frequency of the pulses at the information input of the delay unit 9 and corresponds to this frequency in the digital code.

The generator 7 and the first and second elements OR are intended to provide the readings of the reversible counter 15 values of the average frequency of interference.

When each code operation is received, the received number of pulses is reproduced, which is subtracted from the reading of the reversing counter 15. If the frequency of the interfering pulses at the information input of the delay unit 9 changes, then the reversible counter 15 increases its contents as the average frequency of the interfering pulses increases or decreases as this frequency decreases, the delay time does not change. Therefore, the binary code of the reversible counter 15 continuously monitors the average frequency of interference pulses at the information input of the delay unit 9. The binary code from the outputs of the reversible counter 15 is fed to the output of the signal Interference frequency of the device for receiving self-synchronizing and optical sequences and can be used to indicate the frequency of interference, and, if necessary, it can be used to turn off decoder 6 at high interference intensity.

The pulses from the output of block 9 of the delay of the third synchronizer pass, arrive at the element And 20 and the clock input (recording on the falling edge) of the D-flip-flop 21, to the D-input of which the signal “Log. 1, to the control input of the device for receiving self-synchronizing pulse sequences. To the reset input of the D flip-flop 21, the second synchronizer 12 receives pulses from the generator 7, i.e., information pulses. The signal from the single output of the D-flip-flop 21 is fed to the element And 20. With the help of the D-flip-flop 21 and the element And 20, the signal pulses and signal pulses are subtracted from the mixture. The subtraction is carried out because the pulses of the signal and interference mixture on their falling edge energize the D-flip-flop 21 and the next pulses of this mixture begin to pass through the AND 20 until the next pulse clears the D-flip-flop 21. This frequency subtraction process is provided the fact that the used pulses are unsynchronized with each other and the frequency of the mixture of signal pulses and interference is always higher than the frequency of the signal pulses p. Thus, at the output of the element 20, only interference pulses are generated. These pulses on the additional element OR 19 are added to the constant frequency of the pulses from the second output of the distributor 5. At the output of the additional element OR 19, the total frequency P + Pen is formed. This frequency arrives at the clocking of the delay unit 10. The input of the last and the summing input of the additional reversible counter 16 receives pulses of the signal E from the second synchronizer 12. The pulses from the output of the delay unit 10 through the additional synchronizer 14 are fed to the subtracting input of the additional reversible counter 16, which forms a code corresponding to the frequency at the input of the additional block 10 delay to the frequency at its clock input. Adding a constant frequency Pei, to the frequency Rl, is necessary for the delay unit 10 to delay even in the absence of interference pulses Pd, which is necessary to eliminate the possible overflow of the additional reversing counter 16 in this case. Thus, the frequency of the ROL is taken into account. unchanged, the reading of the additional reversible counter 16 is directly proportional to the signal / noise ratio. Moreover, since the additional corresponding reversible counter 16 is preliminarily recorded with a code corresponding to a predetermined signal-to-noise ratio, as the signal-to-sound ratio increases, the additional reversible counter code 16 exceeds the initial code, and when the signal-to-noise ratio decreases, it is smaller than the initial code.

Code additional reversive counter 16 is fed to the Converter 8,

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the voltage at the output of which chutes the threshold of the amplitude quantizer 1 in accordance with the actual signal / noise ratio. If the actual value of the signal r is exceeded, the signal / sy. given its value, the converter 8 produces a voltage that reduces the threshold of the amplitude quantizer 1, and vice versa, with a smaller value of the actual value of the signal-to-noise ratio, the converter 8 produces a voltage that increases the threshold. The distributor 5 generates time-shifted synchronization pulse sequences that control the first 11, second 12 and third 13 synchronizers and the additional synchronizer 14 to eliminate the imposition of synchronized pulses on top of one another. Divider 4 is used to match the delay time in delay unit 9 with the input signals.

Claims (1)

Invention Formula A device for receiving self-synchronizing pulse sequences, containing serially connected amplitude quantizer, converter signal duration-number of pulses, first synchronizer and reversible counter, serially connected clock generator, frequency divider, delay unit, decoder, first element OR, pulse generator, second synchronizer and the second OR element, the output of which is connected to the subtracting input of the reversible counter, are connected in series pulse distributor and the third synchronizer, information input and output of which is 1: connected to the auxiliary output of the delay unit and the second input of the second element OR, as well as converter code voltage, output of the clock generator connected to the pulse distributor, the second and third outputs of which are connected respectively to the clock inputs of the second and third synchronizer. the information input of the amplitude of the 1st quantizer, and the outputs of the decoder in,; are the input and output of the device, respectively, characterized in that. In order to improve noise immunity, a D-flip-flop, an element I, an additional power supply unit, an additional synchronizer and an additional reversible counter are introduced, the outputs of the additional reversible counter through the converter code - voltage are connected to the control input of the amplitude quantizer, the second output of the distributor pulses connected to the second input of the additional element OR and the clock input of the additional synchronizer, the output of the second synchronizer is connected to the information input of the additional delay unit, the summing input of the additional reversible counter and the reset input of the D-flip-flop, the clock input of which is combined with the second input of the And element and connected to the output of the third synchronizer, and the enable input of the recording of the additional reversible counter Connected to the reset input of the reversible the counter, the write enable input and the information inputs of the additional reversible counter, the D-flip-flop D input and the outputs of the reversible counter are respectively the write enable input, the Signal to Noise Ratio input, the control input and the output of the Interference Frequency signal.