SU1591004A1 - Adder - Google Patents

Description

The invention relates to automation and computing. 'The purpose of the invention is to reduce hardware costs. The device contains a converter of 1 binary code into a compressed code, a group of elements I 2, a block 3 divisions into two in a compressed code, a group of delay elements 4.1 sludge.

Z. · "1591004 A1

eight

3

1591004

four

The invention relates to automation and computing and can be used in information processing systems when implementing technical means of digital computers and discrete automation.

The purpose of the invention is to reduce hardware costs.

The drawing shows a block diagram of a summing device.

The device contains a binary code converter 1 into a compressed code, a group of elements AND 2. A unit 3 divisions into two in a compressed code, a group of elements 4 delays. The unit 3 divisions into two in the compressed code consists of a group of elements AND 5, a group of elements BANKS b and an element OR 7. The device has 8 inputs, a synchronization input 9 and an output 10 of the sum. The first group of inputs of the converter 1 binary code in the compacted code is connected to the inputs 8 of the device. The first inputs of the elements And 2 are connected to the input 9 of the synchronization, and the second inputs with the corresponding outputs of the converter 1 of the binary code into the compressed code. The outputs of the elements And 2 are connected to the corresponding inputs of the unit 3 division into two in a compacted code. In block 3 division into two in the compressed code, the output of the element OR 7 is the output of the remainder of the block 3 and connected to the output 10 of the device’s sum, the inputs of the OR element 7 are connected to the outputs of the corresponding BAN 6 elements, the outputs of the And 5 element are connected to the inputs of the corresponding delay elements 4, information inputs of the BANNER 6 elements are connected to the first inputs of the corresponding Ibi elements connected to the corresponding odd inputs of block 3, the control inputs of the BANKS B elements are connected to the second inputs of the corresponding Ibi elements under lyucheny to respective inputs of even block 3.

The device works as follows.

The inputs 8 are received the same digits of all terms. Starting with the lower ranks. Converter 1 converts the binary code arriving at its inputs into a compressed code, which, through elements 2, enters the inputs of block 3 divisions into two in a compressed code during a clock pulse at input 9. The resulting quotient, through elements 4, of delays enters the second group of inputs of converter 1 binary code in the compacted code along with the following bits of the incoming components. At output 10, the next discharge amount is formed. Total number

the ticks of the sum is equal to

t = n + [1od (N * 7/4)],

where η is the word length of the terms;

N is the number of terms.

Let it be necessary to sum up the following seven terms: 010110, 101011, 011011,111111,101110,110011,101010. The processed sections at the inputs 8 have the form 0111010, 1111.111, 1001100, 111101, 1011010, 0101111. At the output of the converter 1, the processed sections have the form 0001111, 1111111, 0000111, 0011111, 0001111.0011111. During the first clock pulse applied to the synchronization input 9, the subdivisions of the addends, i.e., 0001111, are supplied to the input of the 3 division block into two in the condensed code. As a result of the conversion of this code, block 3 generates a partial 0011, which through delay elements 4 arrives at the second group of inputs of converter 1, and the remainder, equal to “0", without delay, goes to output 10. During the second pulse, fed to synchronization input 9, the code equal to 00111111111 composed of private 0011 and second is input to converter 1 discharge th cutoff terms, ie code 1111111. It is converted to code 00111111111, which, acting on the input of block 3 divisions into two, is converted to a quotient equal to 001111. And the remainder equal to "1" goes to output 10, forming the second digit of the required amount. During the third pulse fed to the synchronization input 9, to the input of the converter 1 is fed a composite slice from the received private and third processed slice 0011110000111. The binary code converter converts it into the compressed code word 0000001111111, which is fed to the input of the 3 division unit by two in the compressed code, corresponding to at the output of the unit, 0000111, the remainder of which ”1” is the third digit of the required amount.

Similarly, the device continues to work until receiving the tenth digit amount. The sum code in this case is 100100110. In the eighth and ninth cycles, zero codes are received at the inputs 8 of the converter 1.

Claims (1)

A summing device comprising a binary code converter into a compressed code, a group of elements AND, a division unit into two in a compressed code, a group of delay elements, with the first group 5 1591004 6 two in the compressed code are connected to the inputs of the group delay elements, characterized in that, in order to reduce hardware costs, output residue block divide by two in the compacted code is connected to the output of the sum of the device, and the outputs of the delay elements of the group are connected to the second group of inputs of the binary-to-code converter. The inputs of the binary code converter to the compressed code are connected to the inputs of the device's components, the first inputs of elements AND groups are connected to the synchronization input of the device, the second inputs to the outputs of the binary code converter to the compressed code, and the outputs to the inputs of the division unit by two in the compressed code, the outputs of the integer part of the result of the division unit by