JPS6217828A - Data conversion system - Google Patents

Abstract

PURPOSE:To reduce the load of data processing based upon a processor by shifting digital data in plural ranges (conversion ranges) obtained from an A/D converter to a prescribed direction by the number of bits corresponding to the ranges and then inputting the shifted data to the processor. CONSTITUTION:An analog signal 1 is inputted to the A/D converter 3 and the converted parallel digital signal 2 and converted unit information 5 are outputted. The signal 2 is set up in a register 6 in a data conversion part 14. The information 5 is inputted to a shift pulse generating part 8 and shift pulses P corresponding to the conversion unit are outputted. Consequently, the data in the register 6 are shifted by the number of the shift pulses P and complement information F outputted from a complement generating part 15 is set up in the register 6. Thus, the value of the analog signal 1 is found out by the processor 4 on the basis of the product of the shifted digital information 9 and the number of shift pulses P.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a system in which an AD converter that outputs digital data of multiple ranges (conversion ranges) and a processing device are connected, in which digital data from the AD converter is output to the processing device. When inputting the digital data to the input device, the digital data is shifted in a predetermined direction by the number of bits corresponding to the range and then inputted, thereby reducing the data processing load on the processing device.

[Industrial application field]

The present invention relates to an improvement in a data conversion method for converting output data of an AD converter into data according to its conversion unit.

It is desired to improve processing efficiency when receiving and processing digital data from an AD converter that outputs data in multiple ranges.

[Conventional technology]

A conventional example will be explained using figures. FIG. 4(a) is a block diagram explaining a conventional example, and FIG.
3 is a data block diagram illustrating the configuration of a parallel digital signal 1) output from a converter 3. FIG.

In FIG. 4 (al), when the conversion unit designation information 5 is sent from the processing unit 10 of the processing device 4, the AD converter 3 converts the analog signal 1 into the digital signal 1 in the designated unit.
) and output in parallel.

At this time, the AD converter 3 outputs the control pulse P for the same month, and the parallel digital signal 1) is thereby set in the register 6.

The parallel digital signal +1 is as shown in Fig. 4 ibl.
It is an 8-bit signal and does not indicate the type of conversion unit.
? ◇Information G (2 hits), code information S (2 bits).

)-) and data l') (4 bits). As shown in Figure 4+bl, D consisting of digits Wf 1-fa, 9D, i.e. t'>2(t! [IIJ T' ] OO]
The value of J differs depending on the value of conversion succession information i[IG.

That is, the value (for example, voltage value) of the data digit position (lowest digit position) r+ differs as follows depending on the value of G (00 to 1).

(G) (Voltage value) (Volt) +1 3 In other words, the value of the data D is determined by the value of the conversion unit G.

Therefore, when this parallel digital signal 1) is processed by the processing unit IO, the calculation unit 12 converts the value of the data D based on the converted sheep position information G4 from the discrimination unit 13, that is, the data D
Calculate the value D° by multiplying the weight of the conversion unit information IG by
This is sent to the processing section 10.

[Problem that the invention seeks to solve]

As is clear from the above, when the parallel digital signal 1) from the AD converter 3 is input to the processor 10, the conventional method has a problem in that an arithmetic processing means is required to convert the data. was there.

[Means for solving problems]

FIG. 1 is a diagram illustrating the principle of the present invention. The present invention provides a system in which an analog-to-digital converter 3 that converts an analog signal 1 into a parallel digital signal 2 and outputs the parallel digital signal 2, and a processing device 4 that receives and processes the parallel digital signal 2, in which an analog quantity is converted into a digital signal. an analog-to-digital converter 3 or a processing device 4 that outputs conversion unit designation information 5 that is converted into a quantity and indicates a conversion unit; a shift register 6 that stores parallel digital signals 2; and a number that corresponds to the conversion unit designation information 5. The shift pulse generating section 8 outputs the shift pulse 7.

(Function) After the parallel digital signal 2 from the analog/digital converter 3Z is stored in the shift register 6, the conversion unit designation information 5 is generated by the shift pulse 7 generated from the shift pulse generator 8. The digital information in the shift register 6 is shifted in a predetermined direction by the number of digits corresponding to , and converted into digital information 9.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram explaining one embodiment of the present invention, and FIG. 3 is a data block diagram explaining one embodiment of the present invention.

In FIG. 2, the AD converter 3 converts the analog signal 1 into
Convert to parallel digital signal 2, parallel digital signal 2
and conversion unit information 5 are output.

It is assumed that the parallel digital signal 2 is composed of a code C (2 bits) and data D (6 bits) as shown in FIG. 3 fal, and the figure shows an example of a negative numerical value.

Therefore, digit positions f7 and f8 of code C contain binary information “1”.
" is output. Note that binary information "0" is set in digit positions fII and f in FIG. 3 fa+.

The parallel digital signal 2 is set in the register 6 of the data converter 14. The shift pulse generator 8 outputs shift pulses P having the following number of pulses according to the contents of the conversion unit information 5.

[Conversion unit] [Shift pulse] (Volt) (Pieces) For example, in Figure 3 (b) where the conversion unit information 5 specifies the unit of 2 volts
The focus is shifted one focus to the right as shown by l, and the complement information F from the complement generator 15, ie, binary information "1", is placed in the digit position f8.

Figure 3 (C1 shows an example where the conversion unit is 1 volt. In this case, the shift pulse generator 8 outputs two pulses P in succession. The data in register 6 is shifted two bits to the right, and binary information rlJ is placed in digit positions f7 and f8.

The processing device 4 can obtain the value of the analog signal 1 by multiplying the shifted digital information 9 by a constant value (1 in this example). For example, when the analog signal σ) is 114 volts and the conversion unit is 2 volts, the output from the AD converter 3 is "1) 100100" and the output from the shift register 6 is rlllloooloJ (- in decimal notation).
14).

■When the analog signal is 17 volts and the conversion unit is 1 volt, the output from AD converter 3 is N1'100100J, and the output from shift register 6 is [1)1)0010J
(meaning -7 in decimal).

In the embodiment, the AD converter 3 outputs the conversion unit designation information 5, but in the case of an AD converter that does not have a means to output the conversion unit designation information 5, the broken line in FIG. As shown, this conversion unit designation information 5 is sent from the processing device 4.
By outputting , it is possible to perform exactly the same control operation.

As described above, the present invention shifts the output (parallel digital) signal from the AD converter 3 by the number of digits corresponding to the conversion unit in the shift register 6, and sends the shifted information 9 to the processing device 4. It was designed to This reduces the load on the processing device.

〔Effect of the invention〕

The present invention has the advantage of eliminating the need for input data discrimination processing in a processing device and improving processing efficiency.

[Brief explanation of drawings]

Figure 1 is a principle diagram explaining the present invention. Figure 2 is a block diagram explaining an embodiment of the present invention. Figure 3 is a data block diagram explaining an embodiment of the present invention. Figure 4 is a conventional diagram. A block diagram explaining an example, 1 is an analog signal, 2, 1) is a parallel digital signal, 3 is an analog-to-digital (AD) converter, 4 is a processing device, 5 is conversion unit specification information, 6 is a shift register, 7 is a A shift pulse, 8 a shift pulse generation section, 9 information after shifting, 1O a processing section, 12 an arithmetic section, 13 a discrimination section, 14 a data conversion section, and 15 a complement generation section.

Claims (2)

[Claims] (1) In a system in which an analog-to-digital converter 3 that converts an analog signal 1 into a parallel digital signal 2 and outputs it, and a processing device 4 that receives and processes the parallel digital signal 2 are connected, an analog quantity is converted into a digital quantity. An analog-to-digital converter 3 that outputs conversion unit designation information 5 that specifies the conversion unit to be converted, a shift register 6 that stores parallel digital signals 2, and a shift pulse 7 that outputs the number of shift pulses 7 that corresponds to the conversion unit designation information 5. After the parallel digital signal 2 from the analog-to-digital converter 3 is stored in the shift register 6, the shift pulse 7 generated from the shift pulse generator 8 generates conversion unit designation information 5. A data conversion method in which digital information in a shift register 6 is shifted in a predetermined direction by the number of digits corresponding to , and converted into digital information 10. (2) The data conversion method according to claim 1, comprising a processing device 4 that outputs the conversion unit designation information 5 and an analog-digital converter 3 that outputs only the parallel digital signal 2.