GB2145889A - Analog-to-digital conversion - Google Patents

Abstract

A successive-approximation type of analog-to-digital converter which, to increase the effective conversion rate, comprises a series of comparison stages C1 -C8 operable, on a pipeline basis, to form respective bits of a digital signal corresponding to a received analog signal. The first stage C1 compares the received analog signal A with a fixed reference VF and, depending on the result of the comparison, generates an appropriate bit value (to register DR1) and passes on to the next stage by means of analog register AR1 either the same value of analog signal or the difference between that value and the reference. Each subsequent stage, apart from the last, carries out the same operation vis- à-vis the analog signal passed to it by the next preceding stage. The last stage C8 carries out a comparison operation and generates a bit value (to register DRS) but of course does not need to pass on any analog signal. The comparison signals fed to the respective stages may be in binary sequence (as shown) or may be all the same in which case an analog signal doubling element is provided between each two adjacent stages (Fig. 2). <IMAGE>

Description

SPECIFICATION Analog-to-digital conversion The well known successive-approximation method of analog-to-digital conversion, wherein a single comparator is used to build up a digital signal one bit at a time by successive comparisons between the received analog signal and an analog signal corresponding to the digital signal so far built-up, may be somewhat limited in speed. The also known flash conversion method, wherein the analog signal is compared simultaneously with a series of reference values by a corresponding number of comparators and the comparator outputs combined by a logic circuit, is faster than the successive approximation method but the apparatus for carrying it out is expensive and tends to load the analog signal quite heavily.It is known to reduce the cost of a flash converter by carrying out the conversion using two stages, one carrying out a rough flash conversion and forming the most significant half of the eventually required digital signal, and the second stage forming the less significant half of the eventual digital signal by flash converting the difference between the original signal and an analog signal corresponding to the digital signal provided by the first stage. US Patent Specification No.

4,326,1 92 discloses a successive-approximation analog-to-digital converter operating on a pipeline basis, the successive comparisons being made by respective ones of a series of comparators arranged such that the successive comparators operate simultaneously on successive samples of the analog signal. As in the usual successive-approximation method, in each case, the comparison is between the analog signal sample and an analog signal formed by converting the digital signal as it has so far been built up. Thus, for each stage of the pipeline, there is required a logic circuit operable in response to signals received from earlier stages to produce one of a series of digital signals and a digital-to-analog converter for forming the comparison signal to be applied to the comparator for that stage.

According to the present invention, there is provided an analog-to-digital converter comprising a series of comparison stages operable, on a pipeline basis, for forming respective bits of a digital signal corresponding to a received analog signal, the first stage being operable for comparing the received analog signal with a fixed comparison signal and each subsequent stage being operable for comparing an analog signal, derived by the preceding stage or stages from the received analog signal, with a fixed comparison signal.

A converter in accordance with the invention, may as regards its pipeline basis have certain similarities to the apparatus disclosed in US Patent Specification No. 4,326,192 but, instead of generating a particular reference signal in each stage dependent upon the digital signal so far built up, the analog signal itself is modified in its passage through the pipeline while the comparison signal for each stage is fixed. In one embodiment to be described, only a single fixed reference signal is required for all stages.

Reference will now be made, by way of example, to the accompanying drawings, in which Figs. 1 and 2 are simplified circuit diagrams of respective embodiments of an analog-to-digital converter in accordance with the invention.

The analog-to-digital converter of Fig. 1 is operable to produce a series of eight-bit digital signals D corresponding to respective successive samples of an analog input signal A having a value in the range 0 to VF volts. The signal A is fed to the first of a series of seven identical pipeline stages (only the first three of which are shown) each comprising a comparator amplifier C1, C2, C3 and so on for the successive stages, an eight-bit wide digital register DR1, DR2, DR3 and so on, and an analog register AR1, AR2, AR3 and soon.

The last of the seven stages is connected to an output stage comprising a comparator amplifier C8 and a digital register DR8 as before but not an analog register. Each analog register and each digital register is supplied with clock pulses from a common clock signal source (not shown) while the inverting inputs of the comparator amplifiers are fed with respective ones of a series of comparison voltage values derived from a resistor chain connected between ground and a voltage reference source (not shown) providing a voltage equal to the full-scale voltage VF of the signal A. The resistor chain is such that the respective values of the comparison voltages fed to the comparators C1 to C8 are VF/2, VF/4, VF/8 and so on, according to a binary scale down to VF/256 for the comparator C8 in the last or output stage.

Each analog register comprises a clock input for the aforementioned clock pulses, a control input and two analog signal inputs AN.IN and REF. The comparison voltage applied to the comparator in each of the first seven stages of the converter is also fed to the signal input REF of the analog register in the same stage. Under the control of the clock signal, samples of either the instant voltage value appearing at the input AN.IN of the analog register or that value minus the comparison value appearing at the input REF, which being dependent upon the value of the signal applied to the control input, are latched into the register.

The input signal A is applied to the noninverting input of the comparator C1 and to the input AN.IN of the analog register ARi. If the signal A is greater than VF/2, the comparator C1 produces a high (logic value '1') output which is latched into the high order bit position of register DR1 by the clock signal.

At the same time, the value of the signal A minus the comparison value VF/2 is latched into analog register AR 1. Alternatively, if signal A is less than VF/2, comparator C1 produces a low output (logic value '0') which becomes latched into register DR1 and which so controls analog register AR1 that signal A is latched therein unchanged, ie without having VF/2 subtracted therefrom.

The value latched into analog register AR 1 is applied to the non-inverting input of comparator C2 and the input AN.IN of analog register AR2 in the second stage of the converter which operates in the same way as the first stage, namely, depending upon whether the value then stored in register AR2 is greater than or less than the comparison value VF/4 applied to the inverting input of comparator C2, the latter produces a iogic '1' or logic '0' output which becomes latched in register DR2, in this case into the second highest order bit position of the register while the highest order bit is latched in from the first stage register DR 1, and which controls analog register AR2 so that there is latched therein either the output of register AR1 unchanged (if the comparator output is 'O') or the output of register AR1 minus VF/4 (if the comparator output is '1'). Each subsequent stage of the converter also operates in the way described for the first and second stages, each adding a respective bit to the digital signal and each, depending upon the value of that bit, passing on to the next stage (where there is one) either the analog signal sample which it received or that sample minus the value of the associated comparison value.The input to the first stage, ie the signal A, is in the range 0 to VF and is compared with VF/2 to produce the highest order digital signal bit, the input to the second stage is always in the range 0 to VF/2 and is compared with VF/4 to produce the second highest order bit, the input to the third stage is always in the range O to VF/4 and is compared with VF/8 to produce the third highest order bit and so on until, in the output stage, a sample in the range 0 to VF/128 is received and compared with VF/256 in order to produce the least significant bit of the digital signal.

Although the digital signal corresponding to any one sample of the signal A is built up over a series of successive clock cycles as in a known successive-approximation converter with a single comparator, while any one stage of the converter is operating on that sample, the other stages are operating on respective successively preceding or following samples, ie a new sample is accepted into the converter and a new digital output signal becomes available from it at each clock cycle. Thus, the converter as described can operate significantly faster than the known successive-approximation converter. Meanwhile, for a given number of bits of the digital output signal, it may comprise fewer components than a flash converter. Also, the illustrated converter does not comprise any digital-to-analog converters of the kind used in US Patent Specification No. 4,326,192.

As will be realised although the digital registers DR1 to DR8 may be identical, ie each with a capacity of eight bits, this would only be in order to render the first seven stages of the converter of uniform construction and hence possibly make it easier to construct the converter as a whole. In fact, the register DR1 only needs to have a one-bit capacity, the register DR2 a two-bit capacity and so on. Only the register DR8 requires a full eight-bit capacity. Clearly the register in each stage could comprise only the capacity needed for that stage. The function of each of the registers DR1 to DR7 at least is mainly to impose a one clock cycle delay in the passage of the digital signal bits-possibly, therefore, the registers could be replaced by other devices able to provide this delay function.

Each analog register device AR1 to AR7 may comprise a suitable analog storage element together with a suitable logic gating circuit at its input for receiving the clock signal and control signal and, in dependence upon the control signal value and at the instance of the clock signal, causing either the analog signal received at its input AN.IN or that signal minus the signal received at its input REF to be stored in the storage element.

The converter of Fig. 2 is like that of Fig. 1 except that an amplifier having a voltage gain of two is arranged before the input AN.IN of each analog register in the second to seventh stages of the converter. Meanwhile, a single common comparison value VF/2 is fed to the inverting input of each of the amplifiers, and to the input REF of each analog register.

Consideration of Fig. 2 will show that it operates similarly to Fig. 1 except that the analog values latched into the analog registers and hence passed on to the non-inverting inputs of the respective comparators are always in the range 0 to VF.

Figs. 1 and 2 each show an eight-bit converter but clearly there could be more or less than eight stages to provide a digital signal with correspondingly more or less than eight bits.

The illustrated converters could be implemented as made-up circuits using discrete components or printed circuit boards or could be partially or wholly condensed using large scale circuit integration techniques, for example in the form of a monolithic silicon 'chip'. The analog registers could form a kind of analog shift register based on the known 'bucket brigade' technology. As a further possibility, each analog register could comprise an arrangement of one or more track and hold amplifiers. Preferably, each register would comprise two such amplifiers arranged in parallel to form a kind of analog flip-flop with one amplifier sampling the input signal at any particular time and the other outputting the previous sample.

Claims (5)

1. An analog-to-digital converter comprising a series of comparison stages operable, on a pipeline basis, for forming respective bits of a digital signal corresponding to a received analog signal, the first stage being operable for comparing the received analog signal with a fixed comparison signal and each subsequent stage being operable for comparing an analog signal, derived by the preceding stage or stages from the received analog signal, with a fixed comparison signal.

2. A converter according to claim 1, wherein the comparison signal associated with any one of said subsequent stages has a magnitude equal to one half the magnitude of the comparison signal associated with the next preceding stage, and wherein the analog signal received by each said subsequent stage from the next preceding stage has a magnitude equal to one of either the magnitude of the analog signal received by that next preceding stage, or the difference between that magnitude and the magnitude of the comparison signal associated with that next preceding stage, which being dependent upon the result of the comparison in said next preceding stage.

3. A converter according to claim 1, wherein all the stages are supplied with the same comparison signal and wherein the analog signal received by each said subsequent stage from the next preceding stage has a magnitude equal to one of either twice the magnitude of the analog signal received by that next preceding stage or twice the difference between the comparison signal and the analog signal received by said next preceding stage, which being dependent upon the result of the comparison in said next preceding stage.

4. A converter according to claim 1, 2 or 3, wherein each stage apart from the last comprises a comparator amplifier connected to receive the analog signal and comparison signal associated with that stage, digitial register means connected to the output of the comparator amplifier, and analog signal register means for making available to the next subsequent stage the analog signal associated with that next subsequent stage.

5. An analog-to-digital converter substantially as hereinbefore described with reference to Fig. 1 or Fig. 2 of the accompanying drawings.