SU1587527A1 - Device for interfacing memory of collective use - Google Patents

Abstract

The invention relates to computing and can be used to create multiprocessor systems with shared memory. The aim of the invention is to improve the speed when accessing a shared memory memory by combining the writing process in one of the processor interfaces with the writing or reading process in another processor interface. This goal is achieved in that the device comprises a control unit 1, the first and second switches 2 and 3, the first and second nodes 4 and 5 of the address identification, the first and second address inserts 6 and 7, the first and second interface blocks 8 and 9, the first and the second registers 10 and 11, the third and fourth switches 12 and 13. 2 Cp f-ly, 3 ill.

Description

This completes the exchange of the memory management device with the collective memory in the Record mode w

Resetting the shift register 40 (Fig. 2) of the control device 1, the first 23 and second 24 flip-flops results in the output of the second 37 element fQ that AND-OR signal of the logical zero, which resets the third trigger 25, which in turn blocks the passage through the first element AND 27 .. signals of the clock generator 38 to the input jj of the synchronization register 40 shift.

The logical zero signal from the output of the first element AND-OR 36, resulting from zeroing the fourth

consequently, at the first input above the element And 61, leads to the left at the output of the last signal, a logical unit.

The leading edge of the signal from the output of the sixth element 61 is the recording of register mode 57 and the recording of the first register 10 of the interface with the memory of the col- lective use (Fig. 1).

In the first register 10 you write the address from the input 15 of the address and the signal Read from the input 16 of the mode of the first processor interface.

Zero digit register 57 p

th bit of the shift register 40, followed by the JQ of the first interface unit 8

(Fig. 3) a logical is written, and in the first bit a logical signal is read from the input 73 of the first interface unit 8

The leading leading edge of the clock signal will be recorded in the fourth trigger 26.

By writing zero to the fourth 26 trigger, the reset signal is removed at the first 25 inputs of the first 32 and second 33 OR elements, and hence at the reset outputs of the first 23 and second. 24 flip-flops and a reset signal is removed at the reset input of shift register 40.30 i Clearing the signal of the logical unit at the end of operation 70 of the first interface unit 8 (Fig. 3) removes the reset signals at the reset inputs of the sixth 58 trigger and register 57 re - press and through the second element NOT 67 unlocks the sixth element And 61.

Thus, all elements of the mouth (Fig. 3) are recorded in a logical unit, and in the first bit a logical zero of the signal is read from the recording input 73 of the first interface unit 8.

Logical signal zero Reading the first input of the third element AND-OR 62 eliminates the high level signal at the output of the last when the third input arrives at the signal of the logical unit from the output of the sixth element And 61.

A logical zero from the output of the third element AND-OR 62 blocks the switch 68.

The low signal level Reading the input of the first element NOT 66 provides at its output the level of a logical unit that is fed to the second input of the element AND 65. At control 1 and the first inter-Qde to the first input of the element 65 of the interface 8 of the block 8 are brought into the initial The state and memory management unit is ready for further slave.

In the Read data mode from the shared memory memory, at the input 15 of the address of the processor interface, for example, the first one, the address of the readable memory cell is set, and at the input

Mode 16 is a Read signal, which is an input signal of the Record signal, and a Marker signal.

After recognizing the shared memory address, the logical unit from the output of the first address recognition node is fed to the input 69 of the nep-v interface unit 8 (Fig. 3) and then to the second input of the sixth Element I 61.

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logical unit from the output of the sixth element AND 61, at the output of the third element AND-NE 65 a logical zero appears, which is fed to the input of the installation in the unit of the seventh trigger 59

The seventh trigger 59 is set to one because, at its input, set to zero, there is a logical unit of the signal. A marker from the input of the marker 72.

The logical unit from the output of the seventh 59 trigger arrives at the fourth input of the third element I-ШШ 62 and at the output 75 of the resolution of the first interface unit: 8,

The high level signal from the output 75 of the resolution of the first interface unit 8 (Fig. 1) opens the third switch 12, allowing data to pass

consequently, at the first input of the sixth element I 61, the appearance at the output of the last signal, a logical unit.

The leading edge of the signal from the output of the sixth element 61 is the recording strobe of the mode register 57 and the recording strobe of the first register 10 of the multi-access memory interface (FIG. 1).

The first register 10 records the address from the input 15 of the address and the signal Read from the input 16 of the mode of the first processor interface.

Zero bit register register 57 of the first interface unit 8

(Fig. 3) the logical unit is recorded, and the first bit is the logical zero of the signal Read from the input 73 of the recording of the first interface unit 8.

Logical signal zero Reading the first input of the third element AND-OR 62 eliminates the high level signal at the output of the last when the third input arrives at the signal of the logical unit from the output of the sixth element And 61.

A logical zero from the output of the third element AND-OR 62 blocks the switch 68.

A low signal level Reading the input of the first element NOT 66 provides at its output the level of a logical unit that is applied to the second input of the element AND 65. When it arrives at the first input of the element And 65 sig

logical unit from the output of the sixth element AND 61, at the output of the third element AND-NE 65 a logical zero appears, which is fed to the input of the installation in the unit of the seventh trigger 59.

The seventh trigger 59 is set to one because, at its input, set to zero, there is a logical unit of the signal. A marker from the input of the marker 72.

The logical unit from the output of the seventh 59 flip-flop arrives at the fourth input of the third element I-ШШ 62 and at the output 75 of the resolution of the first interface unit: 8,

The high level signal from the output 75 of the resolution of the first interface unit 8 (Fig. 1) opens the third switch 12, allowing data to pass

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from the input-output 20 of the device data

for connecting the memory to input-output 14 of the data of the first processor interface.

At the inputs of the control unit 1 (Fig. 2), the following signals are set: a signal of a logical unit at the input 41 of the exchange feature; the signal of the logical unit at the input 43 of the marker, | Q fed from the output of the marker 80 of the first interface unit (Fig. 3); - the signal of the logical zero at the input 44 of the record, supplied from the output 82 of the recording of the first interface unit 8. 15

At the first input of the second element AND 28 of the control device 1 (Fig. 2) there is a logical unit from the input 41 of the exchange feature, at the second input there is a logical unit due to the absence of a signal. The prohibition on input 46 prohibits output 79 of the prohibition of the second interface unit 9 (Fig. 3). with.

The signal of the logical unit from the output 25 of the second element And 28 nearest edge of the signal of the clock generator 38 cocks the first trigger 23.

The logical unit from the output of the first trigger 23 through the first resolution output 53 30 opens the first switch 2 (Fig. 1) and permits the passage to the output 21 of the address written in the first register 10.

The logical unit at the output of the first trigger 23 of the control device 1 (Fig. 2) through the second element OR 33 keeps the second trigger 24, g in the zero state, d (through the third element OR 34 is fed to the seventh input of the second element I-III 37, at the sixth the input of which contains a logical unit .c of the inverse output of the second bit of the shift register 40. This is a condition for the appearance at the output of the second element AND-OR 37 of a logical signal of the logical unit from the direct output of the second bit of the shift register 4 is fed to the first output 51 of the marker block 1 y more systematic way and through the open first switch 2, (Figure 1.) is applied to the device 22 and the mode signal is a unit of the stamp, which is applied to

the reset input of the third trigger 25 and

allows writing to the last logical block.

Which unit is the front (conditionally second). Thus, it is carried out from the front of the clock signal-support signal.

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The leading edges of the signals of the clock generator 38 passing through the first element 27 to the synchronization input of the shift register 40 record and shift the logical unit to the first and then to the second bit of the shift register 40.

The shift of the logical unit in the second bit of the shift register 40 leads to the appearance of a logical zero at the inverse output of the second bit of the shift register 40. A logical zero from the inverse output of the second bit of the 40 shift register is fed to the sixth input of the second element AND-OR 37, which results in the output of the last logical zero, which is fed to the reset input of the third trigger 25 and resets it. A logical zero from the output of the third trigger 25 blocks the passage through the first element And 27 signals of the clock generator 38 to the synchronization input of the register 40 hectares.

Thus, the dip shift of the logical unit to the third and fourth bits of the shift register 40 is stopped.

The leading edge of the logical unit signal from the direct output of the second bit of the shift register 40 to the fifth flip-flop 35 is written down the logical zero of the signal Read from the second output of the multiplexer 39.

At the same time, the low level reading to the second output of the multiplexer 39 passes from the input 44 of the record, since the control input of the multiplexer 39 contains a logical zero from the output of the second trigger 24.

The signal of the logical unit from the direct output of the second bit of the shift register 40 is supplied to the first output 51 of the marker of the control unit 1 and then through the open first switch 2; (Fig. 1) is applied to 22 modes of the device and is a Mar signal.

ra 38.

The logical unit from the output of the third trigger 25 is supplied to the second input of the first element AND 27, allowing the clock generator 38 to pass through the last signal to the synchronization input of the shift register 40.

22 modes relative to the signals at the output 21 of the device address.

After the address appears at the output 21 of the address, the readout signal and the memory marker signal appear at the output of the mode 22, the memory sets the data at the input-output 20 of the data and

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Signal Readiness memory. Data from the input-output 20 of the device data through the open switch 12 passes to the input-output 14 of the data of the first jip-processor interface.

The Readiness signal is supplied to the first. The readiness input 49 of the control unit 1 is as follows (Fig; 2).

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81 of the first interface unit 8 and to the removal of the logical unit at the information input of the sixth trigger 58.

The logical unit from the input 70 of the end of the operation is fed to the second input of the third element AND-OR 62, at the fourth input of which there is

Logical unit Readiness of the memory of logical logic unit from the output of the seventh

trigger 59. Logical units at the second and fourth inputs of the third element AND-OR 62 are a condition for the appearance of a logical unit signal at its output, which is fed to the enable input of the fifth switch 68 and allows the passage of the JJO logical unit from the last information input to the ready output 78 the first interface unit 8.

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The ic of the first ready input 49 is supplied to the fourth input of the second I-III 37 element, on the third input of which there is a logical unit from the direct output of the second bit of the shift register 40. The presence of logical units at the third and fourth inputs of the second element AND-OR 37 is a condition for the appearance at the output of the last signal of the logical unit. The logical unit from the output of the second element AND-OR 37 is applied to the reset input of the third trigger 25, allowing the last leading edge of the signal of the clock generator 38 to write to the last logical unit.

The logical unit from the output of the third trigger 25 permits the passage through the first element AND 27 of the signals of the clock generator 38 to the synchronization input of the shift register 40.

In shift register 40, a logical unit is shifted to the third bit and the signal of the logical unit from the third bit output is applied to the second inputs of the fourth 30 and fifth 31 AND elements, as well as to the first input of the second AND-OR element.

Moreover, the logical unit at the first input of the second element I-ShSh 37 is a condition that confirms the presence of a logical unit at its output

At the first input of the fourth element And 30 there is a logical unit from the output of the first trigger 23 ,. therefore, the appearance at the second input of the fourth element AND 30 of the logical unit from the output of the third bit of the shift register 40 results in the output of the fourth element And 30 of the signal of the logical unit, which through the first output 55 of the operation end of the control unit 1 is fed to the input 70 the first interface unit 8 (Fig. 3).

The signal of the logical unit at the input 70 of the end of the operation resets the mode register 57, which leads to the removal of the signal of the exchange signal at the output

logical logic from the exit of the seventh

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trigger 59. Logical units at the second and fourth inputs of the third element AND-OR 62 are a condition for the appearance of a logical unit signal at its output, which is fed to the enable input of the fifth switch 68 and allows the passage of the JJO logical unit from the last information input to the ready output 78 the first interface unit 8.

The signal from the ready output of the first interface unit 8 (Fig. 1) is a Ready signal from a shared-memory interface device. On a Readiness signal, the processor reads. data from the input-output 14 of the data of the first processor interface and completes the exchange with the shared-use memory in the data reading mode. In this case, the address is removed at the input 15 of the address of the first processor interface, and the Marker signal is output at the input 16 of the C1 mode.

A logical zero at the input 72 of the marker of the first interface unit 8 (FIG. 3) sets the seventh 59 to the trigger, which leads to the appearance of a logical zero at the output 75 of the resolution and at the fourth input of the third element AND-OR 62 blocks the fifth switch 68, which leads to the removal of the Readiness signal at output 78.

Thus, at the input-output 14 of the data (Fig. 1) of the first processor interface, the data is removed (the third switch 12 is closed) and the Readiness is removed.

The shift of the logical unit to the fourth bit of the shift register 40 of the control unit (Fig. 2) results in a signal of the logical unit from the fourth bit of the shift register 40 at the fourth and third inputs of the first AND-OR element 36.

At the second input of the first element AND-OR 36 there is a logical zero of the Read signal written to the fifth trigger 35, therefore the logical unit at the output of the first element AND-OR 36 occurs only when a logical one appears at its first input.

The first input of the first element I-36 is supplied with a signal from the first output of the multiplexer 39, which is the inverse of the signal at the input of the marker A3.

Removal in the first processor interface of the signal The marker results in the appearance of a logical zero at the input of the first input marker 43 of the mode of the control device 1, with the logical unit appearing at the first output of the multiplexer 39 and, as a result, 15 I is the logical one at the exit of the first element AND-OR 36.

The logical unit from the output of the first element AND-OR 36 is fed to the information input of the fourth 26 trigger 20 and the nearest leading edge of the signal of the clock generator 38 will be recorded in a quarter trigger 26.

The logical unit from the output of the fourth 1 trigger 26 resets shift register 25 and 40 through the first element OR 32 resets the first trigger 23, and through the second element OR 33 keeps the second trigger 24.30 in the zero (reset) state.

The reset of the first flip-flop 23 and the bits of the shift register 40 to zero leads to the appearance of a logical zero at the output of the second AND-OR 37 element, which resets the third flip-flop 25. eg the logical zero from the output of the third flip-flop 25 blocks passage through the first 27 of the AND signals So- . 38 of the generator 38 to the input of the register 40 shift 40

Resetting the first trigger 23 and the shift register 40 results in the removal of the resolution signal at output 53, the memory marker signal at output 51 and the removal of the signal of the logical unit at the first 45 output 55 of the end of the operation.

A logical zero from the output of the fourth bit of the shift register 40 gives a logical zero at the output of the first element AND-OR 36, which is followed by the rie -jO low edge of the signal of the clock generator 38 is written to the fourth trigger 26, which leads to the removal of the reset signals 23, second trigger 24 and at the input. “Reset the shift register 40.

A logical zero at the input 7Q of the end of the operation of the first interface unit (Fig. 3) is fed to the input of the second element NOT 67 and the logical unit from the output of the last unlocks the sixth element And 61,

The mode of exclusive access to shared memory by either of the two processor interfaces (for example, the first one) can be initiated both in write mode and in read mode. This mode differs from that described by the fact that if there is a signal. A marker at the input of a marker 72, for example, the first interface unit 8, a logical unit signal appears at the input 74 of a monopoly, which cokes the eighth trigger 60, and no prohibition signal

 at the input 71, the blocking feature from the second interface unit 9, at the output 77 of the blocking and the output 79 of the ban, according to the level of logical zero, which prohibits the generation of similar signals in the second interface unit 9, as well as the input 42 of the ban of the control block 1 (Fig. 2) It prohibits the passage to the elements of the control signal exchange unit 1 from the second interface unit 9 via the input 45 of the exchange indication.

The termination of the monopolistic mode occurs immediately after the removal of the signal of the monopole at the input 74 of the monopoly of the first interface unit 8, i.e. after the end of the required number of calls to the shared memory.

Claims (3)

1. A collective memory interfacing device containing a control unit. The first and second switches, two address identification units, the first and second resolution outputs of the control unit are connected to the resolution inputs of the first and second switches, respectively, first, second and third. the outputs of the first switch are connected respectively to the first, second and third outputs of the second switch and respectively to the data input-output, address output and device mode output, information inputs of the first and AIS torogo node addresses connected respectively to the first and vtorm input device address, characterized in that, in order An increase neither the speed of accessing the par-, five collective use due to the combination in time of the process: notes in one of the processor interfaces with the process of writing or reading in another processor interface, two interface blocks, the third and fourth switches and two register, and the information inputs fQ of the third and fourth switches are connected to the third input-output. the device data, the outputs of the third and fourth switches are connected respectively to the first and second inputs, the data output of the device, the enable inputs of the third and fourth switches are connected to the resolution outputs of the first and second interface blocks, respectively, the first, second and 20 third information inputs of the first the register is connected respectively with the first input-output of the device data, with the first input of the device address and with the nepBbiM input of the device mode, 25 the first, second and third information. The inputs of the second register are connected respectively to the second input-output of the device data, to the second input of the device address and to the second input of the 30-second press of the device, the first, second and Tjpeta outputs of the first register are connected respectively to the first, second and third information inputs of the first switch, the first, second and third s outputs of the second register are connected respectively, with the first, second and third information inputs of the second switch, the recording inputs of the first and) second registers are connected to the outputs before recording Of course, the first and second interface blocks, the address identification inputs of the first and second interface blocks are connected to the outputs of the first and second 45 address identification nodes, respectively; the inputs of the blocking sign of the first and second interface blocks are connected to the blocking outputs of the second and first interface blocks, respectively; JQ modes of the first and second interface blocks are connected respectively to the first and second inputs of the device mode, the outputs of the first and second interface blocks are connected, respectively At the first and second inputs of the control unit mode, the first and second outputs of the operation end of which are connected to the same inputs of the first and second interface blocks, respectively, the ready outputs of the first and second interface blocks are the first and second open outputs of the device, respectively. the outputs of the marker of the control unit are connected to the third informational inputs of the first and second switches, respectively; the first and second inputs of the readiness of the control unit are connected to tr There are informational outputs of the first and second switches, respectively. 2o The device according to claim 1, wherein the control unit comprises a clock generator, a multiplexer, a shift register, five flip-flops, five AND elements, three OR elements, and two I-IC elements, with the output of the clock generator connected to the synchronization inputs of the first, second, third and fourth flip-flops and with the first input of the first element And whose second input is connected to the output of the first trigger, the output of the first element And connected to the synchronization input of the shift register, the reset input of which is connected to the first inputs of the first and second OR with the output of the second trigger, the information input of which is connected to the output of the first AND-OR element, the first inputs of the first and second groups of inputs of which are connected to the fourth discharge of the shift register, the third discharge of which is connected to the first inputs of the second and The third AND elements and the input of the second AND-OR element, the first inputs of the first and second groups of inputs of which are connected to the first and second outputs of the block marker and the output of the POSH shift register, the inverse output of the second bit connected to the first input of the third, group of inputs of the second element AND-OR, the output of which is connected to the reset input of the first trigger, the second inputs of the first, second and third group of inputs of the second element AND-OR are connected respectively to the first input of the unit availability, to the second the input of the ready-to-block unit, with the output of the third element LI, the output of the third trigger is connected b by the third input of the third element SH1K, to the second input of the second element -OR, to the second input of the second element And, and to the first output of the block resolution union of 21 first element OR third element OR third element AND, with the second input with the second input with the second input with the control input of the multiplexer and with the second output of the block resolution, the outputs of the second and third And elements are respectively the first and second outputs of the end of the block operation, the outputs of the first and second OR elements are connected to the reset inputs of the third and fourth triggers, respectively. the triggers are connected to the outputs of the fourth and fifth elements, respectively, and the first inputs of the fourth and fifth elements of and are connected to the corresponding bits of the first and second, respectively About the inputs of the block mode, the second inputs of the fourth and fifth element I are connected to the corresponding bits of the second and first inputs of the block mode, the third inverse input of the fifth element I is connected to the output of the fourth element And, the first inputs of the first and second groups of multiplexer inputs are connected to the corresponding bits of the first input of the block mode, the second inputs of the first and second groups of multiplexer inputs. connected with the corresponding bits of the second input of the block mode, the first inverse output of the multiplexer ene with a second input of first AND input group of first AND-OR, a second input of the second group whose inputs connected to the output of the fifth flip-flop having an information input coupled to a second output multiplexer, the clock input of the fifth flip-flop coupled to a second output bit of the shift register house. 3. The device according to claim 1, characterized in that the interface unit contains a register, three flip-flops, four AND elements, two NOT elements, an AND-OR element and a switch, with the output of the first AND element connected to the register recording input, with the first inputs of the second and the third elements And, with the first input of the first group of inputs of the element I-IPI and with the output , And, ten 15 20 25 And that and e - bjpO p58752722 write block, the output of the second element. And connected to the installation input of the first trigger, the reset input of which is connected to the second input of the second element And with the corresponding discharge of the second input of the mode..block, the output of the first trigger is connected to the first input of the fourth element And, the second input of which. Pogo is the input of the block blocking sign, the output of the fourth element I is connected to the blocking output. the block and with the corresponding discharge of the output of the block mode, the second input of the first group of inputs of the AND-OR element is connected to the input of the first element NOT, with the first discharge of the information input of the register and with the corresponding discharge of the second input of the block mode, the first input of the second group the inputs of the AND-OR element are connected to the reset inputs of the second trigger and register, to the input of the second element NOT and to the input of the operation end of the block, the second input of the second group of inputs of the AND-OR element is connected to the output of the third trigger and to the output of the block resolution, output ele cient AND-OR coupled to the control input of the switch whose output is the output of the readiness of the third flip-flop set input connected to the output of the third AND gate, a second input coupled to an output of the first NOT member, the third flip-flop reset input connected to the input thirty 35 40 45 synchronization of the second trigger, with the first input of the first element And, with the corresponding discharge of the second input of the block mode and with the corresponding discharge of the mode output, the second input of the first element And is the input of the block address identification, the third input of the first element And is connected with the output of the second element NOT, the fourth input of the first element I is connected to the inverse output of the second trigger, the information input of which is connected to the second register output and the corresponding output of the block mode, the first output the register is connected to the corresponding block output mode output. FIG. 2 Phage.Z