SU1550520A1 - Device for interfacing two microcomputers with common memory - Google Patents

Abstract

The invention relates to computing and can be used in two-machine computing complexes with shared memory. The aim of the invention is to increase speed. The device contains matching nodes, address registers, decoding nodes of synchronizing signals, AND, NOT, OR elements, multiplexers, delay elements. 4 il.

Description

The invention relates to computing and can be used in two-machine computing complexes with shared memory.

The purpose of the invention is to increase the speed of the device.

FIG. 1 and 2 show a block diagram of the device; in fig. 3, 4 is the time diagram of the device operation in the mode when the first computer performs a cycle: input - modification - output, and the second computer - Wiod cycle.

Device I is connected to shared memory 2 and contains matching nodes 3 and 4, common buses 5 and 6 of the first and second micro computers, address registers 7 and 8, nodes 9 and 10 of decoding synchronizing signals, IP-12 elements, first and second elements NOT 14 and 15, the second element OR 16, the multiplexer 17, the first and second delay elements formed by keys 18 and 19 and the active-capacitive chains 20 and 21, the first, fifth, eighth, fourth, third, seventh and sixth elements

OR 22-28, the third - the fifth elements are NOT 29-31. General memory 2 consists of two sections 32 and 33 of memory.

The device works as follows.

When the microprocessor system connected to the common bus 5 (6) sets the address on the common bus, it accompanies its installation in the low level of the control signal Om.1 (Od.). On the leading edge of this signal, applied to the control input of register 7 (8), the address bits 1-12 from the common bus 5 (6) are written to the address register 7 (8), the address bits 13-15, which arrive at the information inputs of node 9 (10) are compared at the time of the leading edge of the signal OBm 1 (Rev 2) with the tuning potentials and provided that the address is equal to zero, the signals of the low byte of the memory VKO-1 are generated (VKO- 2) and / or sampling of the high byte of the VK1-1 memory (VK-2). With

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byte operations, depending on the value of the zero-bit address at the time of the leading edge of Obm 1 (Obm 2), are generated by either BKOS or VK1; in word operations, both of these signals are generated simultaneously. These signals are generated by node 9 (10) during the Read (Input) operation with a certain delay relative to the Swap signal, and are removed with a certain delay relative to the trailing edge of the control signal Readings of DFR (DTT2); during the operation Record (Output), these signals are generated with a delay relative to the leading edge of the signal. Data record of the DZP1 (DZP2) is recorded with a delay on the falling edge of this control signal of the bus.

If the signals received from the address bus coincide with the tuning potentials, node 9 (10), which received permission to link shared memory 2 to bus 5 (6), generates a Response (Ot) (Ot2) signal, the leading edge of which is formed upon reaching a certain potential at the delay element 20 (21), the delay time is determined by the resistive-capacitance circuit parameters, which are selected to match the operation of the device with a specific memory. The public key 18 (19) holds a low potential on the capacitor 20 (21) connected to the Entry Delay data entry, Delayed data read node 9 (10).

Capacitor 20 (21) is able to be charged when the internal key of node 9 (10) is locked and when external key 18 (19) is locked. The signal is locked by the internal key of node 9 (10). It is formed with a certain delay relative to the control signals of the DZP1 (DZP2) DTBT1 (DCHT2) bus, subject to the selection of the VKO-1 (VKO-2) and / or BK-1 signals by the 9-unit -I () | external key 18 (19) is locked at the end of the signal. Completed VP1 VP2 of node 3 (4). The Signal Completed is generated when there is a signal Sample Chip VK1 (BK2) at the corresponding input of node 3 (4) of the device.

The outputs of the register 7 (8) address are transferred to the active state at the power of $ 0

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the action of the output signal Res.1 (Dec.2) from the output of the elements is NOT 30 (31).

In the initial state, when none of the microprocessor systems accesses the shared memory 2 registers. 7 and 8 are in the state of the disabled outputs (high-impedance state) due to the low potentials of the signals Dis 1 and Dis 2 from the outputs of the elements NO 30 and 31; there are high potentials at the outputs of the elements OR 25s 26, 23 and 28, since the outputs of the elements OR 16 and 22 have low potentials (the inputs of the elements OR 16 and 22 have high potentials in the absence of the output signals ZKO-1, VK1-1, VKO -2, KBi-2 nodes 9 and 10, and at the inputs of the elements OR 23 and 28 there are high potentials from the outputs. VP 2 node 4 and Bill node 3 are made. High potentials from the outputs of the elements OR 23 (Crystal sampling signals VK1 and VK2 nodes 3 and 4 translate their inputs / outputs into the disconnected (high-impedance) state. Thus, the common Be 2 is disconnected from the shared buses 5 and 6.

If now, for example, the signal OBm 1 (Fig. 2) is received from the first microcomputer, node 9, on condition that the addresses on the common bus 5 match (bits 13-15), with the tuning potentials, generates the signals of VKO-1 and / or BKl-1s arriving at the inputs of the element OR 16 (logical function is indicated for low level signals). High potential from the output of the element OR 16 - enters the input of the element OR 25. At this moment, at the input of the element OR 25 there is also a high potential from the output element OR 23.

At the input of the element OR 25 there is a high potential from the output of Completed node 3, since the Signal Completed at the beginning of the exchange is missing. The coincidence of three high levels of signals at the inputs of the element OR 25 causes the appearance of a low potential at the output, and, as a result, the appearance of a signal selects the BK1 crystal at the input of node 3 and the high signal at the output of the element HE 30e which translates the outputs of register 7 into active mode and connecting the address received from the first shared bus 5 to the address inputs of the shared memory 2 and to the selection inputs of section 32 or 33 of the memory Low to

The potential from the output of the element OR 28, the bistable circuit of the elements OR 23, 25, 26 and 28 will be kept at a low level at the output I and high at the output II to the outputs of the elements OR 25 and 26) until the memory exchange 2 is completed with common bus 5, in spite of the signals that can enter the inputs of the element OR 26 when a common memory 2 is accessed by the second microcomputer. At the same time, a high potential is implemented at the control input of the multiplexer 17, which connects the outputs of the multiplexer with signals from the common bus 5 and from node 9, namely the signals DZGN, DCHT1, VKO-1, VK1-1. The signal from the first output of the multiplexer 17 is the PD / TH signal of the common memory 2 and the switch signal of the information transfer direction (C2) from the common bus 5 to the memory 2. The signal from the second output of the multiplexer 17 is the switch signal of the information transfer direction ( C1) from memory 2 to the common bus, the signals from the first and second outputs of multiplexer 17 are collected on the element OR 24 and gated on the element AND 13 by signals. Completed from nodes 3 and 4 assembled on the element OR 27. The output signal of the element OR 13 gates inverted on u ementah NOT 15 and 29 and passed via multiplexer 17 signals SAI-1 and VK1-1 on the elements 11 and 12 and to form signals referring to younger (IN) and / or over (1) bytes total memory 2.

The bistable circuit is kept in this state until the signal is received (goes into the high level state). The VP1 is output from the node 3 output, which indicates that the transmission of information through the node 3 is completed.

As can be seen from the oscillograms shown in FIG. 2, simultaneously with the operation of the shared memory 2 with the common bus 5, a request arises to exchange with the common memory 2 from the side of the second microcomputer or the active device, i.e. The signals Pm 2 and then DG2 are set to active low. Node 10 generates signals VKO-2 and / or VK1-2, arriving at the inputs of the element OR 22, since the input signal of the element OR 26 has a negative signal VK1 from the output of the element OR 28, bista

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Claims (2)

The mobile circuit is held in a state that provides connection to the shared memory 2 of the first microcomputer. After the transition of the signals VKO-1 and / or VK1-1 from the state of low potential to high at the output of the element OR 25, a high potential is established, which is inverted on the element NEZO. causes a low level signal transition, the low level state, thereby disconnecting the outputs of register 7 from the shared memory address inputs 2. Upon completion of the transmission of information through node 3, which is followed by a transition to the high signal state, Bill is set to high 1 on the exhaust of the element GIS 28, i.e. the high-level signal disables node 3 from shared memory 2, and the presence of three high-level signals at the inputs of the element OR 26 puts its output in a low potential state, which is inverted to. element 31, turns into a high 2 level Dis. This signal switches the address outputs of register 8 to the active state by connecting the address of the common bus 6 to the common memory. 2. The low level of the output signal from the output of the element OR 23 (signal BK2) connects the common bus 6 to the common memory 2 via node 4. Under the action of the low level at the control input to the output of the multiplexer 17 a second group of control signals is connected, namely The DZ2, DZhT2, VKO-2, VK1-2, from which the common memory control signals 2 are formed, are similar to the above. In this way, the second microcomputer (or other active device) accesses the shared memory 2 at the time the first microcomputer performs the modification operation, which 5 increases the overall speed of the system. Upon completion of the operation with the memory of the second microcomputer or active device, similarly to the above, the Split 2 signal goes to low Level 1 — high, and the first microcomputer is able to issue modified data at the previously received address, i.e. complete the operation. Invention Formula thirty 35 0 0 five A device for interfacing two microcomputers with a common memory, containing two matching nodes, the first groups whose information I / Os are the corresponding groups in the device I / O code for connecting the first and second microcomputers to the address and information buses, and the second groups of information inputs / outputs o, form the device’s input-output groups for connecting to the group of information I / O These two registers of the address of the group of information and synchronization inputs of which are respectively groups of inputs and inputs of the device for connection to address information and synchronization buses ad ENA first and second microcomputers and vkodov group form a group of output devices for the connection to the group address inputs of general memory, two node decryption synchronizing signals, the group of information inputs of which are the respective device groups inputs for connection to groups of information inputs of the multiplexer are connected respectively to the first and second inputs of the first and second decoding nodes of the synchronizing signals and groups of device inputs for connecting to the synchronization buses of the first and second microcomputers, the outputs of the matching nodes are connected via the first and second delay elements, respectively The steps of the first and second decoding nodes of the sync signals, the first and second 15 outputs of which are connected respectively to the first and second inverse inputs of the first and second OR elements, outputs connected respectively to the first inputs of the third and 2Q of the fourth element OR, the inverse outputs of which are connected respectively to the first inverse inputs of the fifth and sixth elements OR, and through the fourth and fifth elements NOT to the input groups of address-information and synchronization of reading the second and pergroup of information inputs of the multiplexer are connected respectively to the first and second inputs of the first and second decryption nodes of synchronizing signals and groups of device inputs for connecting to the synchronization buses of the first and second microcomputers, outputs of matching nodes connected, respectively, through the first and second delay elements with the gate signal inputs to the first and second decoding nodes of the clock signals, the first and second e the outputs of which are connected respectively to the first and second inverse inputs of the first and second elements OR, the outputs connected respectively to the first inputs of the third and Q of the fourth element OR, the inverse outputs of which are connected respectively to the first inverse inputs of the fifth and sixth elements OR, and through the fourth and fifth elements NOT to the input The ironing tires of the first and second microcomputers, and the first outputs are the corresponding outputs of the device for connecting the first and second microcomputers to the response buses, three AND elements, two NOT elements and an OR element, characterized in that, 4, to increase the speed of the device, Multiple delays, two delay elements, seven OR elements, and three HE5 elements are inserted in it, the outputs of the higher bits of the first and second address registers are connected to the input of the first element and are the output of the device for connecting to the first input The common memory, & output of the first element is NOT the output of the device for connection to the second sample input of the general memory, the first output of the multiplexer and the inverse outputs of the first and second elements AND are the corresponding outputs of the device for connection to the write-read and sample inputs The low and high bytes of the common memory. The outputs of the second and third elements No. are connected respectively to the first inputs of the first and second elements AND, the second inputs connected to the output of the third element AND, the first and the second 0 five Q five 0 address registers, the output of the first matching node is connected to the first inverse input of the seventh OR element, the second input of the fourth OR element and the second inverse input of the sixth OR element, the output of the second matching node is connected to the second inverse inputs of the seventh and fifth OR element and the second input of the third element OR, the third inputs of the third and fourth elements OR are connected respectively to the inverse outputs of the sixth and fifth elements OR and to the sample inputs of the first and second matching nodes, the first and second transmission direction inputs of which are connected respectively to the first and second multiplexer outputs, controlling the primary input of the fifth OR element connected to the inverted output, the first and second inputs of the third AND element are connected respectively to the outputs of the seventh and eighth elements OR, the first and the second inverse inputs of the eighth element OR are connected respectively to the first and second outputs of the multiplexer, the third and fourth outputs of which are connected respectively to the inputs of the second and third elements NOT. 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