SU1587514A1 - Device for debugging microcomputer - Google Patents

Abstract

The invention relates to computing and can be used in setting up and testing the operation of control microcomputers, debugging and monitoring their software. The purpose of the invention is to expand the functionality of the device by providing additional debugging modes when executing programs and exchanging information. The device contains a control address allocation unit, a mode setting unit, a control unit, a mode analysis unit, a time counting unit, an address and data bus closure unit on a data bus, a programmable delay unit, an interrupt code storage unit, a control information display control unit, a block output of microcomputer operation modes, state indication block, display block. The device makes it possible to increase the efficiency and quality of controlling microcomputers and debugging their software by implementing monitoring and debugging modes with simulating the operation of microcomputers in real conditions. 3 hp f-ly, 10 ill.

Description

The invention relates to computing and can be used when setting up and testing the operation of control microcomputers, debugging and monitoring their software.

The purpose of the invention is to expand the functionality of the device by providing additional debugging modes when executing programs and exchanging information.

FIG. Figure 1 shows a block diagram of a device for debugging a microcomputer at League. 2 is a block diagram of a control address allocation unit; on

FIG. 3 is a block diagram of a time counting unit; in fig. A is the block diagram of the control unit; in fig. 5 - block diagram of the mode analysis block; in fig. 6 is a block diagram of an interrupt code storage unit; in fig. 7 is a block diagram of the block of the address bus and the data bus on the data bus; FIG. 8 is a block diagram of the programmable delay unit: FIG. 9 is a block diagram of the block of operating modes of the microcomputer; in fig. 10 is a block diagram of the control information display control unit.

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The proposed device allows to increase the efficiency and quality of controlling microcomputers and debugging their software by implementing monitoring and debugging modes with simulating the operation of microcomputer in real conditions, taking into account the features of control programs and exchange with external devices. Q

The device contains a block 1 of address control mode address locking, a mode setting block 2, a control block 3, a mode analysis block 4, a time counting block 5, an address bus of f5 address closure 6 and a data bus on the data bus, a programmable delay block 7, interrupt code storage unit 8, control information display control unit 9, block 10 of the Q microcomputer work resins, state indication unit 11, indication unit 12, clock input 13, input 14 of the first exchange signal, command input 15 for command load, ; input signal 16 write-read, 25 input 17 and 4 MHz frequency pulses, output 18 of the exchange signal, clock signal output 19 of the clock, output 20 to the bus was interrupted, output 21 of the initial setup signal of the microcomputer, JQ address bus (ША) and data bus (СД).

The allocation block of the control mode addresses (Fig. 2) contains the register 22, the address selector 23 and the decoder 24. The time counting block (Fig. 3) contains three elements HE 25-27, a counter 28, two AND-elements 29 and 30, two a HE element 31 and 32 and a counter 33. The control unit (FIG. 4) contains a HE element 34, an AND element 35, or an OR element NOT-36-38, three AND elements 39-41, a trigger 42 and a HE element 43. Block analysis of the modes (Fig. 5) contains a delay element 44, two AND-NOT elements 45 and 46, three triggers 47 - 49, a NOT element 50, two elements-d5 and A-NOT 5t and 52, a trigger 53, two elements NOT 54 and 55, AND-NOT element 56 and trigger 57 ..

 The interrupt code storage unit (Fig. 6) contains the register 58 and the AND-NOT element 59. The address and data bus closure unit on the data bus (Fig, 7) contains two registers 60 and 61, and the AND-NE element 62 The programmable delay block (Fig. 8) contains an element, a HE 63, a register 64, a counter 65, an AND-66 element, an AND 67 element and a HE 68 element. The block of micro-computers operating modes (Fig. 9) contains element

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Q

5 Q 5 Q

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five

AND-NE 69, register 70, element AND-NOT 71, amplifier 72 and element AND-NOT 73. The control information display unit (FIG. 10) contains a register 74, a pulse generator 75, a counter 76, two multiplexers 77 and 78, a ditch NOT 79 and 80, switch 81, encoder 82 and decoder 83.

Block 1 of address allocation of the monitoring mode is used to receive address information and select the group of addresses ensuring the operation of the device. Control unit 3 serves to generate signals controlling the operation of other units of the device. The output signals of the block are the signals from the block for selecting the addresses of the control mode and the external input signals for the command load and write-match. The mode setting unit 2 is a device control panel that houses controls and a dial pad in the form of toggle switches and buttons.

The mode analysis block 4 is used to generate signals that ensure the implementation of the corresponding device operation modes. The time counting unit 5 is intended for —account of the program execution time in microseconds or the counting of machine cycles during program execution. Block 6 closure of the address bus and data bus on the data bus provides control information on the tires.

A programmable delay unit 7 is used to receive and store a software settable delay time of an exchange acknowledge signal (second exchange signal). The 8 code storage unit 8 serves to receive information from the mode setting unit or programmatically and output it to the control unit. information and on the data bus. The control information display control unit 9 is intended for switching the input information and generating signals, providing a 1x indication of information on the first display unit. The unit 10 of the operating modes of the microcomputer is used to receive the codes of the operating mode of the microcomputer, including calling certain programs and test procedures specified from the mode setting unit and on the data bus and the state indication unit.

The device works as follows.

When power is supplied to the device in block 2, mode settings are generated, the initial setting signals (Fig. 1) are received in mode analysis block 4, in block 10 of the operating mode of the microcomputer and in block 8 of the exchange store) as follows. At a certain address in the control unit 3, a signal is generated that arrives at the synchronous input of the register 64 of the programmable delay unit 7 (Fig. 8), and the delay code is entered into the register 64 from the data line. On the first exchange signal.

not breaking codes. These signals, which are received from the device input 14, generate the commands for resetting the clock lock mode (output 19), for resetting the counter 28 of the time counting unit 5 (Fig. 3), register 64 and the programmable delay unit 7 ( Fig. 8), the register 70 of the block 10 of the operation modes of the microcomputer (Fig. 9), as well as the initiation of the states indicating indication 11 corresponding to the set operating mode of the LEDs,

From the address bus by the SI sync pulse into the address register 22 (FIG. 2), the address code is entered. Address selector 23 allocates address combinations within limits. At the command of input or output from the microcomputer to the device, input 14 receives the first exchange signal, as a result, the allocated address combinations

the code is stored in the counter 65. With the clock frequency, the value of the delay code in the counter 65 begins to decrease. When resetting the counter 65 at the output 18 of the device, a second exchange signal appears.

The device implements two modes of monitoring the program flow: by counting the program execution time in microseconds and by counting machine cycles. The corresponding mode is specified by the block 2 mode settings. At the same time, for calculating the time from Block 2, the modes are fed to the block 4 of the analysis of the modes, the zero signal is received, and for the counting of machine-based tags, the unit signal. In the case of the choice of the machine clock counting mode, the mode analysis block 4 generates a signal

20

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The time counting block 5 is decoded in the decoder 24. Block 5 and 16 of the microcomputer device are installed at the input of the counter 33 (Fig. 3). Synchro pulses start to flow. The signal is read-write to state 1 when executing the information input command into the microcomputer and into the state O when executing the information output command from the microcomputer.

The closure of the address bus and the data bus on the data bus to ensure control of the exchange channels of the microcomputer is performed as follows.

Register 60 of the address and data register 61 block of the bus of the address and data bus on the data bus 6 (FIG. 7) is constantly inputting information from the I-NE 62 element to the NA and the PC and the data bus from the data bus on command with stepping on register sync inputs. control unit 3. Interpretation of the interruption code According to the corresponding commands from the 3 block from the 8 block of the storage of the interruption codes, information from the register 60. the address or from the register 61 of the data is sent to the SM. At the same time, the information is fed to the input of the register 74 of the block 9

the time counting mode, the input frequency 4 MHz is recalculated in the counter 28 of the time counting unit 5 to the frequency 1 MHz and fed to the input of the counter 33. As a result, the latter counts the time in microseconds. The moments of the beginning and end of the counting in both modes are determined by the signals indicated by the control units 3 and the analysis of the modes 4.

The code of information on interruptions can be recorded in the block 8 of the storage of codes of cracks from the dial-in field of the block 2 of the mode settings or entered in the wires 8 through the AND-HE element 59 of the block 8 (Fig. 6) using signals

50 from the mode analysis block 4 to the distress bus and to the input of the control information display control unit 9 9.

control display of control information (Fig. 10), which provides the ability to visually monitor information on the display unit 12. The rest of the time, the outputs of registers 60 and 61 are in the third state.

Software installation of the delay signal of the exchange quota signal (the second signal

coming from device 14,

the code is stored in the counter 65. With the clock frequency, the value of the delay code in the counter 65 begins to decrease. When resetting the counter 65 at the output 18 of the device, a second exchange signal appears.

The device implements two modes of monitoring the program flow: by counting the program execution time in microseconds and by counting machine cycles. The corresponding mode is specified by the block 2 mode settings. At the same time, for calculating the time from Blok 2 of the modes, a zero signal is sent to the block 4 of the analysis of the modes, and for the counting of machine tags, a single signal. In the case of the choice of the machine clock counting mode, the mode analysis block 4 generates a signal

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The time counting block 5, at which the input of the counter 33 (FIG. 3) of the block 5 starts to receive sync pulses. AT

0

dz gram from the data bus on command from the control unit 3. The interrupt code from the interrupt code storage block 8

the time counting mode, the input frequency 4 MHz is recalculated in the counter 28 of the time counting unit 5 to the frequency 1 MHz and fed to the input of the counter 33. As a result, the latter counts the time in microseconds. The moments of the beginning and end of the counting in both modes are determined by the signals indicated by the control units 3 and the analysis of the modes 4.

The interrupt information code can be written to the short message storage unit 8 from the keypad of the mode setting unit 2 or programmed from the data bus upon a command from the control unit 3. The interrupt code from the interrupt code storage block 8

8 is carried out through the element IS-NOT 59 of block 8 (FIG. 6) by signals

from the mode analysis block 4 to the distress bus and to the input of the control information display control unit 9 9.

Code information on operating modes

the micro-computer is installed on the dial-in field of the block 2 setting modes in the form of a double-byte word and is fed to the register 70 of the block 10 for issuing the micro-computer operating modes (Fig. 9) to the command c

block 4 amaliza modes (Fig. 5). In this case, the device operates in the time counting mode. The control of information from the register 70 of the block 10 of the operating modes of the microcomputer on the main control panel and to the second input of the indication display block 11 is the first from the block 2 of the setting of the modes and from the block 3 of the control. The device has a mode of schenshan | l block 12 of indication of all necessary

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25

thirty

The states of the buttons on the keypad of the block of 2 task modes. In this mode, the microcomputer executes an output command to a specific address, the control signal from control unit 3 arrives at the IS-NE element 73 of the issuing unit for operating the microcomputer 10, and information about the state of the buttons enters the keyboard.

The microcomputer start-up from the mode setting unit 2 is performed in the following manner. On the control panel of the unit 2, the controllers are pressed: the corresponding button (Start), and the signal goes to the unit 4 of the mode analysis through the element 45 to the trigger 53, which goes to the zero state. On a command entry signal, the trigger 57 is set to the zero state, in which case a single sync pulse lock signal appears at the output of the trigger 57 (output 19). The microcomputer starts generating sync pulses.

The microcomputer is stopped from the control panel of the mode setting unit 2 as follows. On the remote control, the corresponding button is pressed, and the signal is fed to the setup input of the trigger 53 of the analysis mode block 4. A trigger 53 is set to a single 40 state, in which case the command load signal (input 15) triggers 57 to single state, and a low level sync pulse signal appears at its output, 45 which blocks the sync pulse in the microcomputer. A microcomputer software shutdown is also provided, while the microcomputer executes the command for outputting a unit to the PC at a certain ad-JQ resolution, and control unit 3 comes to the mode analysis unit 4 to receive control signals.

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information. Information from the block closure. The address bus and data bus of the data lines go through the latter to the register 74 of the display control block 9 of the information 9 (Fig. 10). Further, the information passes to the first multi-lexer 77, the same multiplexer 77 receives information from the block 8 of the stored interrupt codes. Information about the time of program execution is received by the second multiplexer 78 from block 5 of the time count. The control information display control unit 9 receives, switches the input data and controls the output of information to the first display unit 12.

Claims (3)

Invention Formula one . A device for debugging micro-EV containing a control unit, a mode setting unit, a mode analysis unit, a time counting unit, a display unit, with outputs for setting the stop counting modes, the first and second initial settings of the mode setting unit are connected to the first, second, third and fourth blocks, respectively analysis of modes, the fifth and sixth inputs of which are connected appropriately to the input of the device for connection to the output of clock pulses and to the output of the download of the command of the microconfig that is being debugged, the first output of the mode analysis block Connected to the first input of the time counting unit, the first input of the control unit is connected to the input of the device for connecting to the read record output of the microcomputer, characterized in that, in order to extend the functionality by providing additional debugging modes, the device contains a group allocation unit contact mode addresses one . A device for debugging a microcomputer containing a control unit, a mode setting unit, a mode analysis unit, a time counting unit, a display unit, and outputs for setting the stop counting modes, the first and second initial settings of the mode setting unit are connected to the first, second, third and fourth blocks of the unit, respectively analysis of the modes, the fifth and sixth inputs of which are connected respectively to the input of the device for connecting to the output of clock pulses and to the output of the load of the command to be debugged micro computers, the first output of the analysis block mode The first input of the control unit is connected to the input of the device for connecting to the read record output of the microcomputer, characterized in that, in order to expand the functionality by providing additional debugging modes, the device comprises a group allocation unit the addresses of the contact mode of the microcomputer's statutes (transition to the initial program) are performed, the address bus closure block is accessed by pressing the corresponding data button on the data bus, the pad unit on the console The control unit 2 sets the control mode display ki modes. The signal passes to the 3-information block, the programmable back-up block of the modes to the trigger-reset reset input, the code storing block 5148 ra 49 (fig. 5), which goes to the zero state. The signal from the unit flip-flop 49 is fed through the element NOT 55 to the output 21 low level as a signal of the initial setting. The presence of the control information display control unit 9 allows the display on the first l block 12 display all necessary 0 five thirty 40 45 jq 35 information. Information from the block closure-. The address bus and the data bus are sent to the data bus through the latter to the register 74 of the information display control unit 9 (Fig. 10). Further, the information passes to the first multiplexer 77, and to the same multiplexer, 77, information is received from the interrupt code storage unit 8. The program execution time information arrives at the second multiplexer 78 from the time counting unit 5. Block 9 control. displaying the control information receives, switches the input data and controls the output of information to the first display unit 12. Invention Formula one . A device for debugging a microcomputer comprising a control unit, a mode setting unit, a mode analyzing unit, a time counting unit, a display unit, and outputs for setting the stop counting modes, the first and second initial settings of the mode setting unit are connected to the first, second, third and fourth inputs, respectively the mode analysis unit, the fifth and sixth inputs of which are connected respectively to the input of the device for connection to the clock output and to the output of the load of the microconfig command being debugged, the first output of the mode analysis unit The s is connected to the first reset input of the time counting unit, the first input of the control unit is connected to the input of the device for connecting the read record to the microcomputer, in order to expand its functionality by providing additional debugging modes, the device contains an address group allocation unit the control mode, the bus unit of the address bus and the data bus width on the data bus, the control unit for displaying the control information, the programmable delay unit, the block for storing the codes, the unit, the drive unit The operating modes of the microcomputer, the state indication unit, the information input, the clock and exchange inputs of the allocation block of the control mode address group are inputs of the device for connection to the address and control buses of the microcomputer being debugged and the second input of the control unit is the load input devices, the outputs of the allocation block of the group of addresses of the control mode are connected respectively to the input synchronization and resetting of which are connected respectively to the eighth output of the control unit and the third output of the mode analysis unit, the fourth output of which is connected to the blocking input of the time counting unit and is the output of the device for connecting the microprocessor debugging microelectric block to the input, the fifth output of the mode analyzing unit is connected with the enable input of the interrupt code storage unit and in conjunction with the third output of the initial setup of the task block the address strobe and data strobe of the bus of address bus and data bus 15 form the output of the device for the data bus and with the group of inputs of the block to the input of the initial control installation, the first output of which is connected to the input of the mode of the bus of the address bus and the data bus for debugging microcomputer, the sixth output of the mode analysis block is connected to the first information input of the data inn block, the first and second information of the state diction, the second information inputs of which are connected to the device inputs for connecting or to the address and data buses debugged microcomputer, and outputs - to the first input of the control unit infrrmatsionnym The map va 25 for connection to data bus zheniem micro control information and is - roEVM, nine ty yield analysis unit The outputs of the device for connecting to the microcomputer data bus, the output and input of the control unit displaying the control information are connected respectively to the inputs of the display unit and the second output of the control unit, the third and fourth outputs of which are connected to the enabling inputs of the microcomputer operating mode, information ; Inputs and inputs of which are connected to the outputs of the device for connecting the debugging microcomputer to the data bus and the outputs of the mode codes of the computer of the mode setting block, the start and reset start outputs of the computer of which are connected to the same inputs of the mode analyzer, the tenth input of which is connected to the device input Connect - DZ EDR data bus to data bus neither to the microcomputer data bus, but the eleventh, twelfth, thirteenth, and fourteenth inputs — with the fifth, sixth, seventh, and BocbMbw outputs of the block. control, the second output of the ana-50 ™ unit is the input of the device for Modes of operation are connected to the second input of the time counting unit and the enabling input of the microcomputer modes of operation, the installation input of which is connected to the stop output of the mode setting unit, the output of the shuffle code of which is connected to the first information input of the bias code storage unit synchronization and resetting of which are connected respectively to the eighth output of the control unit and the third output of the mode analysis unit, the fourth output of which is connected to the blocking input of the time counting unit and is the output of the device for connecting the microprocessor debugging microelectric block to the input, the fifth output of the mode analyzing unit is connected with the enable input of the interrupt code storage unit and in conjunction with the third output of the initial setup of the task block  form the output of the device for connecting to the initial input; the brains form the output of the device for connecting to the input of the initial installation of the microcomputer being debugged; the sixth output of the mode analysis block is connected to the first information input of the block; its input is connected to the output of the microcomputer operating mode output block, the seventh and eighth outputs of the block Mode analysis are the outputs of the device. The connectors are connected to the reset input of the programmable delay unit, the information input, the enable input and the first 30 second and second synchronous input which are connected respectively with the information output of the bus of address and data bus to the data bus, with the sixth output of the control unit and the device input for connection to the sync and output signals of the exchange of the debug microcomputer connected to the first input of the bus address and data bus closure unit on The data bus of the output of the programmable delay unit is the output of the device for connecting the debugging microcomputer to the input of the sign of the exchange, the second enable input of the closing unit 35 connected to the input of the device for connecting the readout record of the debugging microcomputer, the second information input of the storage unit of interruption codes to the data bus of the debugging microcomputer, and the output to the second information input of the control information display control unit, and is the output of the device for connecting to the output of the disarmed 1 " 1 computer, the third information input of the control information display control unit is connected to you 1587514 The time counting block stroke, the reference frequency input and the sync input of which are connected respectively to the device inputs for connection to the outputs of time stamps and sync pulses of the debugging micro computer. 2. The device according to claim 1, of which is that the control information display control block Q contains a register, two multipliers: a lexor, a pulse generator, a counter, a decoder, two NOT elements, an encoder and a switch, and informational and 12 The modes contain five AND-NOT elements, three NOT elements, five triggers AND a delay element, the first inputs of the first and second AND-NOT elements and the input of the delay element are the seventh input of the block, the reset and synchronization inputs of the first trigger are the third and first inputs of the block, the data input of the first trigger, respectively, is connected to its inverse output and the sixth output of the block, the direct output of the first trigger through the first element is NOT connected to the second out-of-synchronization input of the register is - 5 blocks, the output. The delay units are respectively the first information connected with the second input & the house of the second element input and the record entry of the block, the AND-NOT; whose output is connected to .C. the output of the register and the second information inputs of the reset of the second and third input of the block are connected respectively to the first and second information-20 of the second trigger are the corresponding inputs of the first multiplexer, fourteen and second inputs equal to: the input of which, the first control - switch input, first input the block, the output of the first NAND element is unified with the data input of the second trigger and the eighth output of the block, the element NE, the group of inputs of the decoder and the control input of the second multiplexer are connected to the output counters of the counter i pulses, the outputs of the first multiplexer, the outputs of the second and first elements are NOT connected respectively to the first and second informational and second control inputs of the switch, the outputs of which are connected to the inputs of the encoder, the outputs of which and the outputs of the decoder are are the outputs of an information input of the second multiplexer is on to third ikformatsionnym input unit, and an output connected to the input of a second NOT member. 3. The device according to claim 1, wherein the block of bus closure of the address bus and data bus to the data bus contains the address register, the register register and the NAND element, the information inputs of the address register and the data register being information inputs the block, and the setup and merged inputs of the record are respectively the inputs of the address strobe, data strobe and the input of the block mode, the synchronous inputs of the address register and the data register are connected to the output of the NAND element whose inputs are per50, the output of the block, the synchronous input of the third trigger Is the sixth input of the block, and the output is connected to the fourth output of the block, the reset input of the fifth flip-flop is the ninth input of the block. The first and second block permitting inputs, the address register and register register outputs are the fifth input. The data blocks are informational, the fifth output of the trigger is the unit's block. 4, the apparatus according to claim 1, characterized in that the block is anapirectly, and the inverse through the third element is NOT connected to the fifth output of the block. 12 The modes contain five AND-NOT elements, three NOT elements, five triggers AND a delay element, the first inputs of the first and second AND-NOT elements and the input of the delay element are the seventh input of the block, the reset and synchronization inputs of the first trigger are respectively, the third and first inputs of the block, the data input of the first trigger is connected to its inverse output and the sixth output of the block, the direct output of the first trigger through the first element is NOT connected to the second output, the synchronous input and the installation input 20 of the second flip-flop are respectively the fourteenth and second inputs block, the output of the first element AND-NOT is connected to the data input of the second trigger and with the eighth output of the block, the output of the third element AND-NOT is the seventh output of the block, and its first input is connected to the output of the fourth AND-NOT element and the first input of the fifth the NAND element, the output of which was the 30th output of the block, the output of the fourth NAND element is connected to the third output of the block and through the second element NOT to the first output of the block ka, the second inputs of the first and third elements are NAND integrated and are the twelfth block input, the setup input of the third trigger, the reset input of the fourth trigger and the first input of the fourth element are NAND integrated and are the fourth input of the block, the second input of the fourth AND element is NOT connected to the eighth and eleventh inputs of the block, the data input and the synchronous input of the fourth trigger are the tenth and thirteenth inputs of the block, respectively, and the inverse output is with the second input of the fifth NAND element, the direct output of the second trigger is connected to the third trigger and sixth data input the output of the block, the synchronization input of the third rigger is the sixth input of the block, and the output is connected to the fourth output of the block, the reset input of the fifth trigger is the ninth input of the block. the synchronous input is the fifth input of the block, the output of the fifth trigger is not the synchronous input is the fifth input of the block, the output of the fifth trigger is not mediocre, and inverse through the third element is NOT connected to the fifth output of the block. . 6l ( one 28 / L Sh. tsgz € SP1V rr ic 5 Fmg.b IK1 IR7 QBL9 li ifSH Editor N. Yatsola Compiled by I. Khaeova Tehred L. Serdyukova Order 2421 Circulation 575 VNIIPI State Committee for Inventions and Discoveries at the GKEGG C (JGP 113035, Moscow, Zh-35, 4/5 Raushsk Nab. Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 § Corrector m. Pojo Subscription