SU1691843A2 - Program debug monitor - Google Patents

Abstract

The invention relates to computing and can be used in debugging and monitoring programs, tuning and testing the operation of microcomputers and other computing hardware. The device contains a block for setting modes, an encoder that provides for setting and generating signals to control the modes of operation of the device. The first, second, third, fourth, fifth registers are connected to the data inputs / outputs, memory, device addresses, which allows the exchange of information when executing programs with the display of necessary data on the display unit for monitoring. Register management is effected by a signal from a group of NAND elements, an OR element. By comparing the contents of the first counter with the address of the command executed in the first comparator, tracing the progress of the program is realized. The presence of a block of production of a stop, a block of a record control unit makes it possible to realize the mode of replacing the command of a microcomputer ROM. The generator, the second counter, the decoder provide control of the microcomputer in the process of debugging. The device allows you to improve the efficiency and quality of debugging programs in real time, as well as reliability of operation. 5 il. cl

Description

The invention relates to computing and can be used in debugging and monitoring programs, setting up and testing the operation of microcomputers and other computing devices.

The purpose of the invention is to increase the reliability of the operation of the device due to the organization of blocking the computer clock generator.

FIG. Figures 1 and 2 show a block diagram of a device for debugging and monitoring the progress of programs; in fig. 3 is a flowchart of recording control; in FIG. 4 is a block diagram of the shutdown generation; in fig. 5 - encoder scheme.

The device contains a block 1 setting modes, the decoder 2, the first register 3, the first 4 and second 5 elements AND-NOT, the second register 6, the third 7 and the fourth 8 elements AND-NOT, the element OR-NOT 9, the third 10 and the fourth 11 registers , generator 12, first decoder 13, second 14 and first 15 counters, second decoder 16, stop generation block 17, fifth register 18, second 19 and third 20 one-shot, first 21 and second 22 comparators, third one 23, n an AND-NOT unit 24. A recording control unit 25, a trigger 26, an indication unit 27, an address bus 28, a memory bus 29, a data bus 30, and formational input

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31 from the input source of information from punched tape, information input of 32 clock pulses, input 33 of the command load signal, output 34 of the blocking signal of the microcomputer processor, output 35 of the signal Stop at the input source of information from the punched tape, output 36 of the blocking signal of the micro-computer ROM, input-output 37 address strobe signal, oscilloscope synchronization signal output 38, recording signal output 39, signal output 40 output of the puncture tape information input device, clock lock signal output 41, microcomputer initial setup signal output 42.

The recording control block is formed by the elements AND-NO 43, trigger 44, the element NOT 45, the element 2И-ИИ and 46, two elements AND-NOT 47 and 48, three single-oscillators 49-51, two elements AND-NOT 52 and 53, two element OR - NOT 54 and 55, one-shot 56, element AND-NOT 57, trigger 58 m four elements AND-NOT 59-62.

The stop generation unit consists of three elements OR 63-65, an inverter 66, five triggers 67-71, an element 4I-NE 72 and an element AND 73.

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The block of the encoder contains two formers 74 w 75, ROM 76, four elements AND-NOT 77-80.

The device works as follows.

Depending on the state of the controls of the mode setting unit 1, the device can operate in the following modes:

-Rezhi 1 setting the address of the memory of the micro-computer in the counting addresses 15 of the device with the issuance of it on the address bus;

- the mode of setting data for recording in the microcomputer in the data register 11 of the device with the issuance of this information on the data bus;

- Record mode and record lock in

gdacro computer;

- the mode of replacing one of the microcomputer commands with issuing a replaceable command to the memory bus;

-mode information from the tape;

-coding mode selection punched tape;

- the mode of indication of the contents of the address counter, the data register of the device, ШИ, ШД devices;

- stop mode of punched tape in case of recording error and indication of this stop;

- microcomputer stop mode at the address, idle command (NOP), command load signal and microcomputer clock;

- device start-up mode;

- mode of initial installation and restart of the microcomputer.

To change the contents of the counter 15, the address is needed in block 1 of the task

modes, enter the address input mode and press the buttons on the dial floor of the block 1. At the same time, the information enters the address counter 15 via the shift register 10.

Increase and decrease content

0 counter 15 per unit by pressing the corresponding buttons of block 1.

To change the contents of data register 3, it is necessary to remove the address input mode in block 1 of the mode setting and press the keypad buttons of block 1.

In the case of entering the address, the shift pulses come from element 2ID-NOT 7, and in the case of entering data - from element IIID- HE8.

0 When selecting the mode of transfer of the outputs of the address and microcomputer data to the third state (dir. PD), the data flow through the registers 3 and 18 through the registers 3 and 18 of the data register 3 and the counter 15 of the address.

5 By pressing the record button on block 1

At the output of the recording control unit 25, a recording signal is output to the microcomputer.

In case of discrepancy of information

0, the comparator 22 generates a mismatch signal and the trigger 26 is set to the zero state on the inverse output, and the corresponding LED lights up on the display unit 27. The trigger 26 is set to its initial state by pressing the start button on block 1.

To enter information from a punched tape, you must select the PL mode, the option of encoding punched tapes (dir. ASC) and press

0 KEY on block 1.

A single vibrator 23 generates a pulse for the start of the photo reader. At the same time, code combinations are received at the device input 31, using which the encoder 2 selects

5 data and control signals (address input, frame end, skip and stop). The digital information is entered into the registers of address 10 and data 3. When the encoder 2 generates an address input signal, the code from the address register 10 at the signal from the output of the OR-NOT 9 element is rewritten into counter 15 and goes through the register 18 to the AE. Information from the data register 3 is fed through register 11 to the SD device. By making

5 of the signal of the end of the frame by the encoder 2, this information is rewritten by 1 in the microcomputer at the address set on the IAS. The result of the recording goes to the microcomputer at the overhead line and, in the event of a mismatch, the comparator 22 generates a write error signal by which the trigger 26 is installed. In addition, the AND-24 element generates a pause tape 35 stop signal.

The skip signal is generated by the encoder in order to block writing to the address and data registers at the time of generating the control signals.

Replacing one of the microcomputer commands is performed by dialing the replacement mode on block 1. At the moment when the address 21 selects an address match 21, the information on the output of the address counter 15 with the information on the device MA is output, and the program memory of the microcomputer appears on output 36 of the device and through register 6 on the silo, the code of the tedious command comes from data register 3.

In order to eliminate possible failure situations in the device when executing the replacement mode, it is necessary to arrange a delay in the execution of the program at the time of switching information on the buses. Such delays are effected by generating a lock signal of the microcomputer synchronizer by the recording control unit 25. This signal enters through a stop generation block 17 to the output 41 of the device.

The microcomputer is stopped by the mode setting unit 1. The decoder 13 serves to allocate the idle command code. The generator 12, the counter 14 and the decoder 16 serve to organize the dynamic powering of the control information display unit 27.

Block 17 generation stop working as follows.

By selecting the stop mode at the address and by the arrival of the corresponding signal from the address comparator 21, the trigger 67 is set to zero, the output of element 4IHE 72 is one, which through the IS-NE 73 element enters the output 41 as a zero signal. devices. This signal blocks the operation of the microchip clock generator. The stops in the other three modes (by the stop command, by the command load signal, by the sync pulse) are generated in the same way.

By selecting the setting mode of the address outputs and microcomputer data to the third state (dir. PD), the trigger 70 goes to the zero state, producing a stop signal on a clock pulse.

Upon the arrival of the initial setup signal in the form of a zero, the trigger 71 goes into one state, the output of which sets the triggers 67-70 to the unit state, resetting all the conditions of the microcomputer shutdown.

The stops are also reset by pressing the start button of the device if the mode of transferring the outputs of the address and microcomputer data to the third state is not selected.

The recording control unit 25 operates as follows.

In the case of selecting the transfer mode of the address of the address and data of the microcomputer to the third state (the PD mode is selected and there is no punched tape input mode), to manually record information from the microcomputer, you must press the record button on block 1. At the output of the NAND element 48 is set to a single level and a pulse signal from one of the outputs of the decoder 16 passes through the elements IS-HE 43 and 47, the one-shot 49, the element IS-HE 53 and the one-shot 56. The latter generates a trigger signal for triggering the error 26 and the trigger 58 e through the elements AND-NOT 61 and 62. only one pulse arriving at the output of the recording 39 of the device. Upon release of the record button, the trigger 58 is reset to the initial one state.

At the output of the NAND element 52, a signal is generated, which arrives at the output 37 of the device for synchronizing the address registers in the microcomputer.

The recording signal is also generated in the case where information is being input from a punched tape, and the signal of the end of the frame is input from the encoder 2 to the input of the item IS-NOT 48.

When executing replacement mode on block 1, the corresponding mode is set. At the same time, the output of the element 45 does not establish a single level that allows the single vibrators 50 and 51 to work. At the moment when the information in the address counter 15 and on the AE coincides, the address comparator 21 generates a zero signal. As a result, the trigger 14 is set to the zero state. Single-oscillators 50 and 51 separate the positive and negative fronts of the pulse generated by the trigger 44. The output of the OR-HE element 55 produces zero-level signals that block the microcomputer sync in two cases: when the microcomputer memory is locked and the case arrives at the BMS when register 6 is transferred to the third state and the next microcomputer command is installed on the WB.

At the output of the OR-NOT 54 element, a signal is generated that permits the operation of the N-60 element (with an open collector), the signal from the output of which blocks the memory of the microcomputer.

The signal from the output element AND-NOT 59 allows the issuance of the contents of the register b to the silo.

When selecting the write lock mode, the trigger 58 is set to zero and the write pulse to the output 39 does not pass. The increment signal of the counter 15 per unit is generated on the element 2ILI-2I-I 46 by pressing the record button, the signal from the encoder 2 and pressing the increment button of the address by one.

The signal at the device output 38 is generated at the trigger 44 at the moment the corresponding signal arrives from the address comparator 21.

Thus, the device, in comparison with the prototype, provides an increase in the reliability of operation and a decrease in failures in the mode of replacing the microelement BM command with a device command

The implementation of the device in compliance with the invention makes it possible to increase the efficiency and quality of debugging complex programs in real time by reducing the faulty situations in the mode of replacing the microcomputer command with the device command by generating a clock lock signal at the time of switching information on the memory bus.

Claims (1)

Invention Formula Device for debugging and monitoring the progress of the programs No. 1529227, characterized in that. in order to increase the reliability of operation due to the organization of blocking the microcomputer's synchronous generator, the seventh output of the recording control unit is connected to the twelfth input of the stop generation unit, the recording control unit contains ten AND-NOT elements, two triggers, two IL-AND-NE elements, and 2IL- element 2И-И, four single-vibrators and an element NOT, the first inputs of the first and second elements AND-NOT and the first input of element 2ILI-2I-AND are connected to the first input of the unit, the second input of the second element AND-NOT, the first input of the third element AND -NOT and Torah input element 2or-2I-I coupled to a fifth input of the first and second inputs of the fourth AND-NO elements are connected to the eighth and a ninth input unit and the output - to the second input of the first NAND element, the output of which through the first one-shot is connected to the first inputs of the pbgo and sixth elements of the NAND, the second input of the fifth The NAND element and the third input of the 2ILI-2I-I element are connected to the seventh block input, the output of the i-NE element element is connected to the block input-output and the synchronization input of the first trigger, whose information input is connected to the second block input, the second output element AND-NOT connected to the second input of the sixth element AND-NOT, the output of which through the second single vibrator is connected to the first output block, the synchronization input of the second trigger and the first input of the seventh element is NOT; the information input of the second trigger is connected to the unit potential bus of the unit, and the set and reset inputs - respectively, to the second input of the third NAND element, to the sixth input of the block and to the output of the third NAND element, the direct output of the first trigger is connected to the fourth output of the block, the inverse output of the first the trigger is connected to the start inputs of the third and fourth one-shot and the first inputs of the first element AND LON-NOT and the eighth and ninth element AND-NOT, the second inputs of the eighth and ninth elements AND-NOT and the zeroing inputs of the third and fourth single vibrators are NOT connected to the third input of the block, the fourth input of which is connected to the fourth input of the 2ILI-2I-I element, the output of which is connected to the third output of the block, the inverse output of the second trigger AND -NOT, the second input of which is connected to the output of the seventh AND-NAND element, the second input of which is connected to the output of the third AND-NOT element, the output of the tenth AND-NOT element is connected to the fifth output of the block, the output of the fourth one-vibrator is connected to the first input of the second element IL AND-NOT, the output of which is the seventh output of the block, the output of the third one-shot is connected to the second inputs of the first and second OR-NOT elements, the output of the first OR-NOT element - with the third input of the ninth NAND element, the output of which is the sixth output block, the second output of which is connected to the output of the eighth element AND-NOT. Phys. 1 USA69 and V9 JT dsu Bivgx nc - ate n 1 ЩЩ Щ № ЩО и ЩЩ ivg u / 0 L vg g usd IVQWQ gi vg sho I VQUIQ Om ftU Rezh DDR 1m ) CU Ј0 Re. WP Dir. iff 63 64 55 Re. “G11  si P "t.W WELL Ln Luog fit SU U five D 57 72 58 QB27 $ D c 59 t- S d c 70 TO  WITH four 7 / 5АСО G7 vW Fig lo cu Z3 Ub a