SU1529227A1 - Device for debugging and monitoring program runs - Google Patents

Abstract

The invention relates to computing and can be used in debugging and monitoring programs, tuning and testing the operation of microcomputers and other computing hardware. The aim of the invention is to reduce the debugging time of programs. The device contains a memory block, registers, the first counter, which are connected to the data inputs / outputs, memory, device address, which allows, by setting the mode on the mode setting block, to exchange information during program execution with the purpose of monitoring the necessary data. on the display board. By comparing the contents of the first address counter with the current address of the command being executed, carried out in the first comparison block, a trace of the execution of the program on the LED display panel is implemented. The presence of the write control block, to which commands are received from the decoder block and the mode setting block, allows recording the information in the DVM memory block from an external source and replacing the command in the permanent memory block. A generator, a descrambler counter, and a shutdown generation unit provide control of the operation of the digital computer in the process of debugging. The device allows you to improve the efficiency and quality of debugging complex programs in real time. 2 hp f-ly, 6 ill.

Description

The invention relates to the field of computing and can be used in debugging and monitoring programs, setting up and verifying the operation of microcomputers and other computing hardware.

 The aim of the invention is to reduce the debugging time of programs.

FIG. 1, 2 shows a block diagram of a device for debugging and controlling the course of programs; in fig. 3 - diagram of the display unit; in fig. 4 is a diagram of the mode setting block; in fig. 5 is a diagram of a shutdown generation unit; FIG. 6 is a block diagram of a recording control unit;

The device (FIG. 1) contains memory block 1, first to third registers 2-4, first counter 5, fifth register 6, first comparison block 7, first de

The encoder 8, the first element 2 AND-NOT 9, the third element 2И-НЕ 10, the fourth 1 |) register 11, the display unit 12, the second comparison unit 13, the second element 2ИЕЕЕ 14 quarter ш the element 2Й-НЕ 15, the first fiy element 2ILI-NOT 16, fifth element 1ent 2I-NOT 17, second decoder 18,) setting modes, block 20 you-) operation, generator 21, second-) counter 22, block 23 control recording, trigger . 24, one-shot 25, third decoder 26 first and second information inputs 27 and 28 of the device 10

- 227

addresses 5 of the device data setting mode for writing to the digital computer in the register / data of the device; recording mode and blocking z. the mode is replaced by one of the digital computers; information input mode from punched tape selection mode of punched tape coding; the mode of displaying the contents of the address counter, data register, address input, data and device memory; stop tape mode in case of recording failure and indication of this stop; 1 stop mode of digital computer by address, stop command.

0

20

thirty

35

va, first and second information output | 5 command load signal, device sync steps 29 and 30, device address 31 output, device address 32, device stop output 33, memory lock output 34, address gate 35 , 36 synchronization, 37 signs of device recording, device start 38, device processor lock output 39 / device clock lock output 40, device input 41. device command downloads, device clock input 42, device initial installation output 43, third information input 44 y device, control input j j, 5 of the display unit,

I Display unit 12 (FIG. 3) contains: six multiplexers 46-5.1, de-i encoder 52, board 53 of the segment. Indicator elements of the board 54 light i diodes, i Task block 19 (fig. 4)

contains knot1k "55 typesetting floor,; encoder 56, buttons 57. ,, 67 tasks. modes, the sixth register 68, 69 of the initial setting, buttons for setting the write modes 70, 71 decreasing the address, 72 incrementing the address, 73 start, the initial setting button 74 of the digital computer, trigger 75.

The output unit 20 ((lig. 5) contains three elements IL 76-78, the first element NOT 79, five triggers 80-84, element 4I-NE 85, the second element NOT 86 Block 23 of the control unit (6) contains three element 2I-NOT 87-89, element (2I-2ILI) I 90, three elements 2I-NOT 91-93, trigger 94, element 2IHE 95, trigger 96, element 2I-HE 97,

The device works as follows.

Depending on the state of the controls of the block 19, the device can operate in the following modes: the mode for setting the memory address of the digital computer in the counter

40

45

50

55

pulse CVI; device descent mode; Dir12m initial installation of digital computers,

To change the contents of counter 5, it is necessary at block 19 of setting modes 19 to select the address entry mode and press the buttons of the dialed floor of block 19. At the same time, information will flow into counter 5 through registry 4. You can increase and decrease the contents of counter 5 by one by pressing the corresponding buttons ka 19.

To change the contents of register 2, it is necessary at block 19 of setting modes to remove the address entry mode and press the buttons of the keypad of block 19.

If the address is entered, the shift pulses will come from the output of element 2И-НЕ 10, and in the case of data entry, the output of element 2 И-НЕ 15.

When selecting the transfer mode, the output address and data of the digital computer to the third state will go to the outputs of the address and data through registers 3 and 6, the contents of register 2 and counter 5, respectively, I

By pressing the button 70 of the block 19 at the output of the block 23 a recording signal will be generated, which enters the digital computer,

In the case of information mismatch, data comparison unit 13 generates a information mismatch signal and the three germs 24 are set to zero, with this display unit 12 behind: what is the corresponding LED. The trigger 24. set to the initial state by pressing the button 73 of the device block 19,

To enter information from a punched tape, use button 62 to select the appropriate mode on block 19, button 6, choose the option of punched tape and press

0

0

five

5 command load signal, syncro- 5

0

five

0

five

pulse CVI; device descent mode; Dir12m initial installation of digital computers,

To change the contents of counter 5, it is necessary to select the address entry mode in block 19 of setting modes 19 and press the buttons of the typed floor of block 19. At the same time, information will flow to counter 5 through registry 4. You can increase and decrease the contents of counter 5 by one by pressing the corresponding block buttons nineteen.

To change the contents of register 2, it is necessary in block 19 of setting the modes to remove the address entry mode and press the keys of the dial pad of block 19.

If the address is entered, the shift pulses will come from the output of element 2И-НЕ 10, and in the case of data input, the output of element 2 И-НЕ 15.

When selecting the transfer mode, the outputs of the address and data of the digital computer to the third state will go to the outputs of the address and data through registers 3 and 6, the contents of register 2 and counter 5, respectively I

By pressing the button 70 of the block 19 at the output of the block 23 a recording signal will be generated, which enters the digital computer,

In the event of information mismatch, data comparison unit 13 generates an information mismatch signal and trigger 24 is set to zero, while on display unit 12 for: there is a corresponding LED. The trigger 24. is reset to the initial state by pressing the button 73 of the device block 19,

To enter information from a punched tape, use button 62 to select the appropriate mode on block 19, button 61, select the option of coding punched tape and press

converting hexadecimal numbers into the code of seven-segment indicators, in the mode of indicating the contents of register 2 and the device counter 5 on block 53, the contents of the indicated blocks and the input state are displayed on the button 73 Start button on block 19, the one-one oscillator 25 generates a photo reader start impulse. At the same time, code combinations will come to the device input 28, digital information will be read from the memory block, and decoder codes 8 will allocate codes of cxcih-TjanoB (address input, end of frame, skip and stop), Digital information will be entered In registers 4, 2, Upon generation of address input signal by the decoder 8, the code from the address register will be overwritten into counter 5 and through register 6 it will arrive at the address output. Information 15 from register 2 is fed through register 3 to output 29 of the device data. Upon the generation of the end-of-frame signal by the decoder 8, this information will be overwritten in the digital computer by the address set for the output on elements 9 and 14), and four times during the address. The result of the recording will be received by the bit code of the pressed button, on the digital computer to the memory input and in case of a discrepancy, the data comparison unit 13 will generate a write error signal,

otherwise, the status of the data inputs, the address and the memory is indicated. On a table of 54 LEDs, there are indi cated shutdowns of a digital computer, a unit 20, a device operation modes (from block 19), and a write error signal (from block 24), I..

The operation of the block 19 task modes. By pressing one of the 16 buttons on the keypad, the encoder 56 generates a pulse of positive polarity (after

Pressing buttons 62-67 is fixed in register 68, setting the appropriate operation modes: the input mode to which the trigger 24 is set. The crocks are punched from punched tape; DVR stop mode

In addition, element 2 AND-NOT 17 will be you at the address containing in the counter

work the signal for stopping the punched tape and device address (block 5); the corresponding mode is generated by the LED computer on the stop command; replica 12.

press stop on the boot signal

The skip signal is generated by the 30 commands; the shutdown mode of the digital computer via sync encoder to block writing to the registers at the time of generation of signals: control,

At the stop signal element 2I- NOT

pulse; the mode of displaying the contents of the data register (block 3) and the address counter (block 5) of the device; the address entry mode in the address register 17 is generated by stopping the device's perfole-sa device (block 4); replacement mode

teams of digital computers; write lock mode; select mode of punched tape; the mode of setting the outputs of the address and data of the digital computer to the third state.

you.

Replacing one of the digital computer commands is performed by selecting the appropriate mode in block 19. At the same time, block 7 compares the address. COBdating information at the output of the counter / 5 with information at the input 32 of the device address at output 34 of the device will generate a memory lock command of the digital computer and through register 11 to output 30 of the device the code of the desired command will come from register 2.

The shutdown of the digital computer is carried out by a block of 20 corresponding modes using block 19 ..

The decoder 18 serves to highlight the stop command code.

The generator 21, the counter 22 and the decoder 26 serve to organize a dynamic haul of the display unit 12,

The operation of the display unit 12, With the help of a pattern of multiplexers 46-5 and a decoder 52 in time,

converting hexadecimal numbers to the code of seven-segment indicators, in the mode of indicating the contents of the register 2 and the device counter 5 on block 53, the contents of the indicated blocks are displayed and the input state falls on elements 9 and 14), and the four-digit code of the pressed button,

stupid on elements 9 and 14), and the four-bit code of the pressed button,

otherwise, the status of the data inputs, the address and the memory is indicated. On a table of 54 LEDs, there are indi cated shutdowns of a digital computer, a unit 20, a device operation modes (from block 19), and a write error signal (from block 24), I..

The operation of the block 19 task modes. By pressing one of the 16 keys of the keypad, the encoder 56 generates a pulse of positive polarity (supplied to the elements 9 and 14), and a four-bit code of the pressed key,

Pressing buttons 62-67 is fixed in register 68, setting the appropriate operation modes: input mode of informatronic digital computer by a stop command; re-

press stop on the boot signal

pulse; the mode of displaying the contents of the data register (block 3) and the address counter (block 5) of the device; address entry mode in the address register

Q

0

/

teams of digital computers; write lock mode; , the mode of the choice of coding punched tape; the mode of setting the outputs of the address and data of the digital computer to the third state.

By pressing the buttons 70-73 (respectively, providing the generation of recording signals of increasing and decreasing per unit of the contents of the address counter, the device start signal) by. Their outputs are set to O. In the unpressed state at the outputs of buttons I.

By turning on the power, circuit 69. generates a signal for the initial installation of the device, arriving at register 68 and n at block 20.

Using the trigger 75 by pressing the button 74, the initial setup signal of the digital computer is generated.

--.Work unit 20 generation; stop. By selecting the stop mode at the address and by the arrival of the corresponding signal from the address comparison block 7, the trigger 80 is set to zero, at the output

715

element .85 on Vits 1 and on the output 40 of the device will be installed Oh, blocking the work of the generator sync - g | pulses of digital computers. The stops in the other 4 modes (by the stop command, by the command load signal, by the sync pulse;} are generated similarly,

 At the choice of the mode of setting the outputs of the slot and the data of the digital computer in the third state, the trigger 83 goes to the zero state, generating the stop signal on the clock pulse.

Upon arrival of the initial setting signal, the triggers 80-83 are set to units, thereby dropping; all device stops.

The shutdowns of the devices are also reset by pressing the start button of the device; if the transfer mode of the output of the address and data of the digital computer is not selected, the third state,

Operation of the recording control unit 23 If the output mode of the address and data of the digital computer to the third state is selected, manual recording of the information in the digital computer requires a device record button, and a negative pulse is generated at the output of element 2-NOT 87. field (input mode with a punched tape is not set), This pulse passes through element Z / i-HE 92, enters the synchronization input of trigger 24, upi) goes through element M-HE 95 to output 37 of the device and by moving to 1 in

About sets the trigger 96 to zero, prohibiting the passage of the following impulses Sov. By releasing the record button, the trigger 96 is set to one.

The recording signal is also produced in the case when information is input from punched tapes. The only difference is that a negative polarity pulse is produced at the output of element 2i I-HE 89.

When the write lock mode is selected, trigger 96 is set to zero and the write pulse to device output 37 does not pass. The increment signal of the counter. 5 addresses per unit is generated at element 90 by pressing a button, the signal input from the decoder 8 is pressed and the address increment button is pressed. - a unit.

The signal at the device output 36 is generated at trigger 94 at the instant

7

eight

the input of the corresponding signal from the block 7 cp address.

The command memory blocking signal of the digital computer is aborted from the output of element 2I-11E 97 but received;.: The corresponding signal from trigger 94 and the selection of the command replacement mode IJ, BM,

Claims (3)

Invention Formula Q 0 five 0 35 40 45 50 55  . The device for debugging and monitoring the progress of the program 1) Amm, containing the block of the assignment — mode, the first and second blocks of comparison, the first, second, third and fourth and fifth registers, the first counter, the trigger, the block indica-. In this case, the address input of the device is connected to the first input of the first comparison unit, the output of the first register is connected to the first input of the display unit. cdpi, different teM; that, in order to reduce debugging time, a memory block, a stop generation block, a recording control block, a first, second and third decoder, a pulse generator, a second counter, five 2ii-HE5 elements 21SCH-NOT and a single-shot, and the output of the first counter is connected to the second input of the first comparison unit and to the second input of the display unit, the output of the memory unit is connected to the information input of the first register, the output of which is connected to the information input of the second register and the first input of the second comparison unit, The first output of the mode setting block is connected to the information inputs of the first and third registers, the third register is connected to the information input of the first counter, the output of the first register is connected to the information input of the fourth register, the first information input of the device is connected to the second input of the second comparison unit, the inequality output of which is connected to the information input of the trigger, the second and third information inputs of the device of the connection, respectively, with the first address input of the memory block and the third block display, the address input of the device is connected to the fourth input of the ind; 1Caii block, the second and first information inputs of the device are connected respectively to the first input of the first decoder and the input of the second decoder, the output of which is connected the first information input of the device is connected to the fifth input of the display unit, the second and third outputs of the mode setting block are connected respectively to the sixth and seventh inputs of the display unit, the stop and lock outputs, and the stop output block are connected respectively - DYM inputs of the recording control unit with the eighth input of the display unit / and with the lock output of the device clock pulses, the output of the data format of the task block is connected to the second address input of the memory block and the second | 5 Won, the equality output of the first block by the input of the first decoder, the first, second and third and fourth outputs of which are connected respectively to the first input of the first OR-NOT element, to the first input of the first AND-NOT element, to the 20 synchronization input of the recording control unit and to the first , the input of the second element IS-NOT, the output of the input mode of the mode setting block is connected to the input of the comparison block connected to the eighth input of the recording control block and the clock input of the stop generation block at the address, the outputs of the second and third copies AND-NOT are connected respectively With the recording inputs of the first and third registers, respectively, the output in the left register is the first information output of the device, the output expanding the memory unit and the third input 25 of the pulse pulse generator is connected to the first decoder account, the third output is connected to the first input of the third one by the ninth input of the IS block, the output clock of the task block modes connected to the first inputs of the fourth and fifth elements of the NAND, the outputs of which are connected to the second inputs of the second and third elements of the NAND, respectively, the output of the input mode of the address of the order block of the display and the input of the third de-, encoder, the output of the third desh frat30 is connected to the ninth input of the write control unit and to the tenth input of the display unit, the trigger output is connected to the eleventh input of the display unit and to the second input of the first NAND element whose output is connected to the device, the first output the write control block is connected to the second record register input and is the device memory lock output, the second control block 1 output and record is connected to the counting input of the first counter, the output of which is connected to the information input of the fifth register, th the modes are connected to the second inputs of the fourth and fifth elements of the NAND and the first input of the OR element; the output of which is connected to the input of the first counter recording, the outputs of the punched tape mode, decreasing the address of the stops at the address by the sync pulse, by the command load, by the command code and The output of the initial installation of the mode setting unit is connected respectively to the second input of the recording control unit, to the counting input of the first counter, to the stop inputs by address, sync pulse, command load, operation code, and initial setup input stop generation unit, the output of the blocking mode processor of the mode setting unit is connected to the recording inputs of the fourth and fifth periTTs, to the mode setting input of the stop generating unit and to the third input (the recording control block and the device blocking output, the start of the mode setting unit is connected directly to the start input of the stop generation unit and through the one-shot to the reset input of the trigger and the device start output the output modes of the command change address, write and block address Recordings and restarting output of the mode block J: are connected to the fourth, fifth, sixth and seventh stages respectively, are the output of the device restart, the input of the clock pulses are connected to the clock inputs of the mode setting block and the stop generation block, the equality output of the first block the comparison is connected to the eighth input of the recording control unit and the clock input of the stop generation unit at the address, the outputs of the second and third elements are NOT connected to the recording inputs of the first and third registers respectively, the output of the second register is the first information output of the device, the output of the pulse generator is connected with the counting input of the second counter, the output of which is connected by the ninth input of the unit indication and the input of the third encoder, the output of the third pulse decoder is connected to the counter input of the second counter, the output of which is connected to the ninth input of the block is connected to the ninth input of the write control unit and to the tenth input of the display unit, the trigger output is connected to the eleventh input of the display unit and to the second input of the first NAND element whose output is connected to the device, the first output the write control block is connected to the second record register input and is the device memory lock output, the second control block 1 output and record is connected to the counting input of the first counter, the output of which is connected to the information input of the fifth register, pogo is the device's output output, the third, fourth, fifth and sixth outputs of the recording control unit are connected to the trigger trigger input and are respectively outputs of the device, address synchronization and device recording, the input of the device loading command is connected to the stop input loading instructions of the stop generation unit, the output of the fourth register is the second information output of the device, 2, The device according to claim 1, 1 and 2, and that with the fact that the unit is stop processing contains the first, second, and third elements OR, the first and second elements are NOT, the first, second, third, fourth, and fifth triggers and the AND-NOT element, with the input of the stop modes at the address and operation code unit connected respectively to the first inputs of the first and the second OR elements, from the Q information and the sixth NAND elements, with the information inputs of the first and second triggers, the signs of the stop signs at the address, by the operation code and the load of the block commands are connected respectively to the second inputs of the first and second elements OR, and the second inputs of the third element OR, the output of which is connected to the clock inputs of the second, third and fourth devices, the first input of the third element OR is connected to the clock input of the first trigger, the blocking mode input of the processor block is connected to the input reset the first trigger and information input of the fifth trigger, the output of which is connected to the single inputs of the first, second, third and fourth flip-flops, the start trigger and the initial installation of the block are connected respectively via the first element PE with the clock input of the fifth trigger and the single input of the fifth trigger outputs The first and second elements OR are connected respectively with the information inputs of the fourth and third triggers, the direct outputs of the first, second, third and fourth triggers are connected respectively with ne The first, second, third and fourth inputs of the H – NE element, the output of which is connected directly to the reset input of the fifth trigger and through the second element NOT to the output of the block clock pulses, the direct outputs of the first, second, third and fourth triggers are the block stop outputs, one  3. The device according to 0.1, about tl and h You need to say that the recording control block contains eight INE elements, two triggers and a 2ИЖ-2И-И element, the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth inputs of the block are connected respectively with the first inputs of the first, the second and third elements AND-NOT, with the first input element 2ILI-2I-I, with the first inputs of the fourth, fifth five 0 five 0 five 0 five the first input of the first trigger and the second input of the second IS-NE, the third input of the block is connected to the second input of the 2ILI-2Я-I element, the output of which is the second output of the block, the first input of the block is connected to the second input of the fifth IS-N element and with the third input of element 2ILI-2И-И, the sixth input of the block is connected to the second input of the sixth element AND-NI and to the fourth input of element 2 Ш1И-2И-И, the seventh input of the block is connected to the single input of the second trigger, output: second, right and the sixth elements AND-NOT are connected respectively with the second input p of the first element I-Iffi, with the first input of the seventh element AND-NOT and with zero input of the second trigger, the output of the first element AND-NOT connected to the second inputs of the third and seventh elements of the IS-NOT, the output of which is connected to the first INPUT of the eighth element AND and with the clock input of the second trigger, the output of the third element IS-NOT connected to the clock input of the first trigger, the inverse output of which is connected to the second input of the fourth element IS-NOT, the information input of the second trigger connected to the bus unit potential potential cerned trigger is connected to the second input of the NOR 2I- eighth outputs of the fourth, seventh, third AND-NO elements, a direct output of the first flip-flop and eighth I- NOT element are respectively the first, third, fourth, fifth and sixth unit outputs. Phage.