SU1483457A1 - Microcomputer debugging unit - Google Patents

Abstract

The invention relates to computing and can be applied to control and debug the hardware of a microcomputer and debug programs. The purpose of the invention is to increase the performance when debugging by controlling the hardware of the microcomputer is achieved by looping the program with faulty hardware and by analyzing the retrospective addresses and data and counting the execution time of the program. 1 il.

Description

The invention relates to computing and can be applied to control and debug the hardware of a microcomputer and debug programs.

The purpose of the invention is to increase the performance during debugging by ensuring the control of the microcomputer hardware due to the possibility of looping the program with faulty hardware and due to the possibility of analyzing the retrospective addresses and data and counting the execution time of the program.

The drawing shows a block diagram of a device for debugging a micro-computer.

The device contains the first register 1, the first 2 and the second 3 comparison circuits, the second register 4, the mode setting register 5, the first 6 and the second 7 indication registers, the stack memory unit 8, the address register 9, the counter

10 pulses, the third element OR 11, the trigger 12, the first 13, the second 14, the third 15, the fourth 16, the fifth 17, the sixth 18, the seventh 19, the eighth 20, the ninth 21 and the tenth 22 And, the first 23, the second 24 and fourth 25 OR elements, address input 26, address sign input 27, data sign input 28, control signal input group 29, which includes address and data tracking inputs 27 and 28, device stop signal output 30, interrupt signal output 31 devices, device start 32 input, device clock input 33, device sync output 34, reading input 35 Realty, device start up 36.

Registers 1 and 2. 5 and 9 are device toggle switches.

The device has initial start, stop and interrupt modes and a period mode that is used only

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in combination with the initial start mode.

In the initial start-up mode, the device operates as follows. At the output of the initial start-up of register 5 there is 1. When a pulse signal appears at the input 32 of the device start, the trigger 12 is set to O, while the output 30 of the stop signal is O, and the output 36 of the initial start signal through the elements AND 15 and OR 23 a signal appears and the microcomputer starts the initial start up program. In addition, the signal from input 32 through AND 22 sets counter 0 to O, then, if 1 is present at the output of the countdown indicator of register 5, then the clock frequency is input to the increment input of counter 10 through AND 17, OR 24, and 18 elements from the clock input 33 and the counter counts the program execution time. If, however, the output of the sign of time counting is O, then the signals of the address feature are sent to the input of the element OR 24 through the element 16. 27 and the counter 10 counts the number of exchange cycles on the backbone of the microcomputer. The contents of the counter 10 are indicated on the display register 7. Single signals from the inputs 27, 28 through the element OR 11 are fed to the input 8 of the stack storage record, recording the state of the inputs 26 address-data of the device.

In stop mode, the device operates as follows.

Before starting operation, register 4 records the status indications of inputs 26 and inputs 29. At the output of the register 5 stop mode 1. When a signal combination is set at register 4 and input 29 (the microcomputer can be started, for example, in the initial start-up mode, a single signal appears at the output of the comparison circuit 3, which through the element OR 11 sets to 1 trigger 12. At the output 30 of the stop signal, a single signal appears that causes the microcomputer to stop. The zero signal from the inverse output of the trigger 12 blocks the element And 18, stopping the operation of the counter 10.

After the shutdown of the microcomputer, the trace of the program can be viewed by

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the single block signals to the input 35 of the reading device.

Further control of the microcomputer can be continued, i.e. A new breakpoint has been set. When a single pulse appears at the input 32 of the device, the counter 10 is zeroed through the AND 22 element, and the trigger 12 is set to O, removing the stop signal 30 and thus allowing the microcomputer to continue to work, and the single signal from the inverse output of the trigger 12 goes to the AND 18 element , allowing the counter to work 10.

In the interrupt mode, the output of the stop mode is present O, in register 4 the information about the program interruption point is entered. The interrupt program must be pre-stored in the microcomputer memory.

When a start signal appears at input 32, counter 10 and trigger 12 are zeroed out, removing a stop signal at output 30.

When the microcomputer reaches the register 4, the state at output 31 of the element And 14 appears to be a signal causing the interruption of the microcomputer.

The device can work with the following joint signs of debugging Start-up / Stop, Start-up-interrupt, Start-up-period, Start-up-interrupt-period.

When the device operates in the Initial start-stop mode, single signals are present at the outputs of the stop mode and the initial start mode of the register 5. After starting the device, the microcomputer processes the initial start-up and continues to work until the conditions specified on register 4 appear, after which the operator reads the stack memory 8. The operation of the device in this mode can be performed by setting the output of the time register register 5 as a zero and a single signal. In this case, after the appearance of the stop signal at the output 30, the number of exchange cycles on the microcomputer main line or the time from the moment of start to the moment of stop, respectively, is indicated on the display 7. . WITH

In the Initial start-interrupt mode, a zero signal is set at the output of the stop mode, at the output of the mode

initial start-up of register 5 - single. When the microcomputer is started, the initial start-up procedure is worked out and when a state appears on register 4, the device generates an interrupt signal at the microcomputer at the output 31, which causes the operator-defined program, which can be, for example, the primary or the microcomputer supply program Any program, stitched in the ROM of the microcomputer.

In the mode Start-up-period, the device operates as follows. At the outputs of the initial start-up mode and the period of the register 5 there are 1 in the register 9, the program execution time code or the code of the number of exchange cycles on the microcomputer main line (if there is 1 or 0, respectively, the output of the register time indicator 5) is entered in the register 1 sync.

When a signal appears, the Start at the input 32 at the output of the element OR 25 through the element AND 20 appears which records the contents of register 9 in the counter 10. At the output 36 of the device, a signal appears causing the microcomputer to start. The decrementing input of counter 10 through the element AND 19 from the output of the element OR 2 receives pulses, which are either the signals accompanying the address from input 27 (through element 16) or the clock signals from input 33 (through element 17) depending on the signal at the output of the register count time indicator 5. When the microcomputer performs a specified number of exchange cycles or after a predetermined time has elapsed, a single signal appears at the zero output of the counter 10, which through the AND 21 element and the OR 25 element again puts the contents of the register 10 into the counter 10 and 9 and through the element OR 23 restarts the microcomputer. The process then repeats.

The proposed device allows 45 to debug both the software and hardware of the microcomputer, as it allows cycling the operation of the device with the defective hardware and observing the operation of the device at the various control points on the oscilloscope screen with the required resolution. It should be noted that the prevailing amount. in hardware faults

In addition, when the device data addresses appear on inputs 26 and control signals inputs 29, a combination of signals set to the microcomputer register appears at initial re 1, the output of the comparison circuit 2 does not allow a correct generation. A single signal, which is a command, and therefore not allowed to enter output 34, synchronizes the operation of the device and can be used programmatically.

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with, for example, to synchronize an oscilloscope.

Information about the code stored in register 9 (the return point) and the code stored in register 1 (the synchronization point) is selected by the operator as a result of the analysis of the operation of the microcomputer (analysis of the stack memory 8) in

0 Initial start-stop. In this case, the return point must provide the output of the microcomputer to the incorrectly executed part of the program, and the synchronization point may be

5 for example, the address code of the last correctly read command.

Thus, on the oscilloscope, all internal signals of the microcomputer can be viewed and the cause of the malfunction detected.

The initial start-interrupt-period mode differs from the previous mode in that the interrupt code is preliminarily entered in register 4 and when a combination of signals corresponding to the code in register 4 appears on the main line of the microcomputer, a single signal appears at the interrupt output 31 calling transition to the program previously stored in the RAM. This interrupt program is directed to the wrongly executed part of the program.

This mode is used if failures are fixed in that part of the program, the transition to which is accomplished on any complex devices, or if the faulty part of the photon is not located directly behind the program of the initial start-up of the microcomputer.

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The proposed device allows debugging of both the software and hardware of the microcomputer, as it allows cycling the operation of the device with the defective hardware and observing the operation progress at various test points on the oscilloscope screen with the required resolution. It should be noted that the prevailing number of hardware malfunctions

The microcomputer appears during the initial start-up, which does not allow the command to be executed correctly, and therefore does not allow the device to loop around programmatically.

In addition, the device allows determining the retrospective addresses and data on the microcomputer backbone on a given event and controlling the duration of the execution of a given part of the program, which increases debugging performance.

Claims (1)

Invention Formula A device for debugging a microcomputer} containing the first and second registers, the register of the number of commands, the mode register, the first and second comparison circuits, a pulse counter, ten AND elements, four OR elements, and the information outputs of the first and second registers are connected to the first inputs respectively, the first and second comparison circuits, the address input of the device is connected to the second inputs of the first and second comparison circuits, the equality output of the second comparison circuit is connected to the first input of the first element 1, And, the output of the stop sign The mode setting reference is connected to the inverse input of the second element AND, the output of the third element AND is connected to the first input of the first element OR, the outputs of the fourth and fifth elements AND are connected respectively to the first and second inputs of the second element OR, I differ in that improving performance during debugging, a stack memory block, first and second indication registers are entered into it, the device’s input input is connected to the information input of the first indication register and to the information input of the stack memory For example, the input of the device data tag is connected to the clock input of the second comparison circuit and with the first input of the third OR element, the output of which is connected to the recording input of the stack memory, the sign input of the device address is connected to the second input of the third OR element, to the clock input of the first circuit comparison, with the direct input of the fourth element I, the output of the indication of the stop of the mode setting register is connected to the second input of the first element I, the output of which is connected to the single trigger input, / the equality output of the second circuit compared to e Yu 15 20 25 30, Q five five 0 It is connected to the direct input of the second element I, the output of which is the interrupt output of the device, the start input of the device is connected to the first input of the third element I and to the first input of the trigger, the direct and inverse outputs of which are connected respectively to the stop output of the device and to the first input the sixth element And, the output of which is connected to the summing input of the pulse counter, the output of the second element OR is connected to the second input of the sixth element And, and to the first input of the seventh element And, the output of which is connected to the subtrac one pulse counter, the outputs of the register of the number of commands are connected to the information inputs of the pulse counter, the information outputs of which are connected to the information inputs of the second display register, the read input of the device is connected to the read input of the stack memory unit, the output of the initial start attribute of the mode register is connected to the second input of the third element And, the output of the sign of the periodic control of the mode setting register is connected to the second input of the seventh And element, the first inputs of the eighth and ninth And elements, and with the inv By the tactile input of the tenth And element, the output of which is connected to the reset input of the pulse counter, the overflow output of which is connected to the second input of the ninth And element, the start input of the device is connected to the right of the tenth And element and the second input of the eighth And element, the eighth outputs And the ninth elements And are connected respectively to the first and second inputs of the fourth element OR, the output of which is connected to the clock input of the pulse counter and the second input of the first element OR, the output of the time register control feature Modes connected to the first input of the fifth AND gate and an inverted input of the fourth AND gate, the clock input device is connected to the second input of the fifth AND gate, the output equation of the first comparison circuit is the output of the synchronization output of the first OR gate is the output of the initial starter.