SU1138804A1 - Device for debugging programs - Google Patents

Abstract

DEVICE TO DEBUG PROGRAMS containing the register of the zone's initial address, the register of the zone's final address, the number register, the first, second and third comparison schemes, nine AND elements, three OR elements, the first NOT element, the control register, three groups of AND elements and the first group the OR elements, and the information codes of the initial zone address register and the final zone address register are connected respectively to the first inputs of the first and second comparison circuits, the outputs of which are connected respectively to the first and second outputs of the first And, the information output of the number register is connected to the first information input of the third comparison circuit, the output of the sign of the address of the control register number is connected to the first input of the second element And the first inputs of the AND elements of the first group, the output of the sign of the address of the command of the control register is connected to the first input of the third the element AND the first inputs of the elements AND the second group, the output of the code of the command code of the control register is connected to the first input of the fourth element AND and the first inputs of the elements AND the third group The output of the code sign of the number of the control register is connected to the first input of the fifth And element, the output of the indication of the code indication of the number of the control register is connected to the first inputs of the sixth and seventh And elements, the outputs of the second, third and fourth And elements and the outputs of the And, first, second and second elements of the third group are connected respectively with the first, second and third inputs of the first OR element and with the first, second and third inputs of the IPD elements of the first group (L output of the first OR element is connected to the clock BxcjftoM of the third circuit compared and, the second information input of which is connected to the output of the elements OR of the first group, the output of the first element AND is connected to the first input of the eighth element AND, the inputs of the sign of the number address, the sign of the next command, the sign of the command, the code of the address number, the code of the command address, 00 and the sign of the number of devices connected to the second inputs of the second, third and fourth elements, respectively, with the second inputs of the elements of the first, second and third groups and the second input of the pt element of And, the outputs of the sixth and seventh elements in AND is connected respectively to the first and second inputs of the second OR element, the input of the code of the device command address is connected to the second information inputs of the first and second comparison circuits, characterized in that, with

Description

in order to save memory and increase performance when debugging, a display register, a register for setting number codes, a register for setting counter codes for a cyclove register for an unprogrammed command, a quarter and a five comparison circuit, a clock distributor are entered into the device; cycle counter, encoder ring SGBIG register, second and third elements NOT, quarter and fifth elements ORIR fourth, :: 1, one and sixths of AND group, the second group of elements OR and three elements AND, and the output of the second element OR is connected to the first inputs 7 (s of the elements of the fourth group of which the rpyiuia of the outputs is connected to the information module f by the input of the display register, the input of the code of the device number is connected to the second inputs of the elements of the fourth group and the first group of the output groups of which are connected and with the first information input of the fourth comparison circuit J, the information output of the numbering codes assignment code connects to the third information input of the reference circuit driver, the output of the sign of the number code of the control jiGi-nij: connected to the first inputs of the tenth, eleventh and twelfth elements And second element and element of the group, the output of the sign of the control register address} ;; laziness c.oeiuiHeH with the second inputs of the sixth and tenth elements K; output pr; -; the sign of the register command address is controlled by the connection of the second inputs of the seventh and on the eleventh element and the output characteristic of the control register command code -soedinen with vgorm entrance dvenadn.atogo elements, Ta, and outputs Setting the time counting; , account settings failures; setting the counting of the control point signals, the output of the sign of failure, the output of the characteristic, the control point, the stop mode and the cycle mode of the control register are connected to the first inputs

corresponding to the third, the fourteenth, the fifteenth, the sixteenth, the seventeenth, the ninth, and the second-and-second element, AND, the output T of the retrigger element OR is connected to the first input of the nineteenth element if and through the first element NOT to the first input of the twentieth and t; vadtsat first elements And the output of the third

The comparison circuit is connected to the third inputs of the sixth and seventh elementons Ir, the second inputs of the nineteenth and twenty first elements Id, the outputs of the thirteenth, fourteenth and fifteenth elements And are connected respectively to the first, second and third input-i of the fourth element OR, the output of which is connected to - input of the cycle counter and through the second element NOT - with the clock input of the fifth comparison circuit, the output of the counter characteristic of the cycle of the control register cycles is connected to the first input of the twenty-second element AND, codes twenty The first, nineteenth, twentieth, twenty-second, sixteenth and seventeenth elements And are connected respectively to the first, second, third, fourth, fifth and sixth inputs of the fifth OR element, the code of which is connected to the second input of the eighth element And, the output of the fourth comparison circuit connected to the third input of the nineteenth element I and the second input of the twentieth element I, the output of the eighth element I connected to the second inputs of the ninth and eighth elements AND, whose inputs are connected respectively to the clock input the ring shift register and the first inputs of the elements And with the control of the group, the output of the register of the non-limited command is connected to the second inputs of the elements of the sixth group, whose codes are connected to the first inputs of the elements OR of the second group, the information output of the ring shift register is connected to the input of the encoder, the output of which connected to the second inputs of the OR elements of the second group, the outputs of which are the codes of the unprogrammed device command, the start input of the loop counter, the clock input, the fault input and the control input The second points of the device are connected respectively to the second input of the thirteenth element I, the clock input of the distributor of clock pulses, the second inputs of the fourteenth and sixteenth elements And and the second inputs of the fifteenth and seventeenth elements And, the first and second ports of the clock distributor are connected respectively to the third input of the thirteenth element And and the third entrance of the nine elements And,

The second output of the clock pulse distributor is connected to the third input of the eighteenth element I, the output of the control register stop mode is NOT connected to the fourth input of the eighteenth element AND via the third element, the first and second information inputs of the fifth comparison circuit are connected respectively to the output of the register for setting the codes

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the cycle counter and the output of the cycle master; the output of the fifth comparison circuit is connected to the second input of the twenty-second element AND, the outputs of the tenth, eleventh and twelfth elements of AND are connected to the coil (respectively to the first, second and third inputs of the third OR element, the output of the fifth element I is connected to the clock input of the fourth comparison circuit.

The invention relates to computer technology, in particular, to devices for controlling the course of the injection process, and can be used in the development and debugging of computer programs. A device for debugging programs by stopping a computational process is known, comprising first and second comparison circuits, first and second registers, command number register and operand register, first and second mask registers, setting part of the information participating in the comparison, AND element, comparisons and stop signal generator f. With the help of this device, it is possible to debug programs by stopping the program at particular points for certain values of the operands. However, this requires a large number of shutdowns, which leads to a significant lengthening of the debugging process. It is impossible to debug programs in real time in this way, since shutdowns lead to loss of input information and distortion of the processed data. In addition, this device does not allow the automation of the debugging process, since after stopping the computational process, manual intervention is required to read the information of interest and restart the computer. The closest in technical essence to the invention is a device for interrupting during debugging programs, containing the first, second and third registers, the first, second and third comparison nodes, the group of OR elements, the first, second and third OR elements, the control register, the first, second, and third groups of elements And, the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth elements of AND, and the element NOT. This device can work in one of three modes. In mode 1, when writing to a cell whose address matches the address typed on the toggle register, the device detects a signal at the output that enters the computer interruption system whose program is being debugged. Modes 2, 3, and 4 differ from mode 1 only by not comparing the address of the cell being written to with the contents of the toggle register, but the address of the command being executed, the number of the general-purpose register to which the information is written, or transition commands for each individual mode respectively. The signal from the computer device, the programs of which are to be debugged, terminates the operation and makes a call to the wedge (auto-discontinuous) program, which, depending on the debugging task of the programmer, performs predetermined actions 23. The drawbacks of the known device are the necessity to allocate a computer memory for storing the technological debugging (auto-discontinuous) interrupt response program due to the lack of the possibility of inputting the programmed commands into the computer, as well as the lack of simultaneous accounting of the compatible debugging features of the BHeiLHHx accounting system events, quality and time evaluations and dynamic indication of the contents of operands in the process of debugging programs, which significantly reduces the operator’s labor productivity in developing programs and tladke. The purpose of the invention is to save memory and power, debugging performance ,. The goal is achieved by the fact that device 5 contains the register of the zone's initial address, the zone's final address register, the number registrar, the first, second and third cf. avneni circuit, nine elements AND three elements OR the first element is NOT control register, three the groups of elements And and the first group of elements IlJIPL, moreover, the information, io-1: are NULLO; YOU register the initial address of the zone and the register of the final address of the zone are connected, respectively, with the first inputs of the first and second comparison circuits whose outputs are connected with the first and second the inputs of the first element AND, the information output of the register number — with the first information input of the third comparison circuit; the output of the control register number — with the first input of the second AND element and the first inputs of the AND group of the first group, sign a; with the first input of the third element And and with the first inputs of the element And the second group, output ;; the code of the command of the control register with the initial input of the fourth And element and with the first inputs of the AND elements of the third group; The output of the sign of the code of the number of the control register is connected to the first 1-1 input of the fifth element I, the code of the indication of the code indication of the number of the control register — to the first inputs of the sixth and seventh elements AND, the outputs BTOiJorOj of the third and fourth; the first, second and third groups correspond to: but with the first one, the second m third input; 1, the first ILE element and the nepBi iM5 second and third inputs of the OR elements of the first group, the output of the first Sh1I element with the clock input of the third circuit comparison, the second information input which connects with the outputs of the elements OR of the first GROUP 5, the output of the first element AND - with the first input of the eighth element AND, the inputs of the sign of the address of the number, the sign of the address of the command, the sign of the commandj, the code of the address number, the code of the address of the command, the code of the sign and the sign of the number of the device . the second, third and fourth elements are And, with the second inputs of the elements And the first, second and third groups and the second input of the fifth element And, the outputs of the sixth and seventh elements And - respectively with the first and second inputs of the second element. OR, code input, command addresses — with the second information inputs of the first and second comparison circuits, the indication register, the number code register register, the cycle counter code register register, the unprogrammed command register, a fourth; and fifth comparison circuits, clock distributor, CYCLOG55 counter encoder, ring shift register, second and third KE elements, fourth and fifth OR elements, fourth, fifth and sixth elements of the Ela group: -1eng AND, the second group of OR elements thirteen elements And, moreover. The second element OR is connected to the first inputs of elements AND of the fourth group, the output group of which is connected to the information input of the display register, the input code of the device number to the second inputs of elements AND of the fourth group and to the first inputs of the elements And p of the group whose outputs connected to the first information input of the fourth comparison circuit, the information output of the register setting codec number with the second information input of the fourth comparison circuit, the output of the code indicator of the number of the control register with the first the inputs of the tenth, eleventh and twelfth elements I and the second inputs of the elements of the fifth group, the output of the sign of the address of the number of the control register — with the second inputs of the sixth and tenth elements and the output of the sign of the address of the command of the control register — with the second inputs of the seventh and one And elements, the output of the code of the command of the command register of the control register - with the second input of the twelfth element And, the outputs of the installation of the time account, the INSTALLATION of the failure account, the installation of the account of the control point signals, the output of the sign of failure, the control point, the stop mode and the cycle mode of the control register are connected to the first inputs of the thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, ninth and eighteenth elements AND, the output of the third element OR, and the first element NOT with the first inputs of the twentieth and twenty-first elements And, the output of the third comparison circuit - with the third inputs of the sixth and seventh elements And, the second inputs of the nineteenth and twenty-first elements And, outputs t the eleventh, eleventh and fifteenth And elements - respectively with the first, second and third inputs of the fourth OR element, the output of which is connected to the counting input of the loop counter and through the second element. NOT - with the clock input of the fifth circuit compared, the output of the counter characteristic of the cycles of the control register cycle - with the first input of the twenty second element AND, the outputs of the twenty-first, nineteenth, twenty-second, sixteenth and seventeenth elements AND, respectively with the first, second, fourth, the fifth and sixth inputs of the fifth OR element, the output of which is connected to the second input of the eighth element AND, the fourth output of the comparison circuit with the third input of the nineteenth element AND and the second input of the twentieth element And, the output of the eighth element AND - with the second inputs of the ninth and eighteenth elements I, the outputs of which are connected respectively to the clock input of the ring shift register and the first inputs of the elements AND of the sixth group, the output of the unregistered command register — with the second inputs of the elements of the sixth group whose outputs are connected to the first inputs of the elements. Win of the second group, information output of the ring shift register - with the input of the encoder, the output of which is. connected to the second inputs of the OR elements of the second group, the outputs of which are the outputs of the unprogrammed device command, the cyclo counter start input, the clock input, the fault input and the control point input of the device are connected to the second input of the thirteenth element, the clock input of the clock distributor, respectively the inputs of the fourteenth and sixteenth elements And the second inputs of the fifteenth and seventeenth elements And the first and second outputs, the clock distributor, respectively with the third input of the thirteenth element I and the third input of the ninth element I, the second input of the clock distributor - with the third input of the eighteenth element I, the output of the control register stop mode is NOT connected to the fourth input of the eighteenth element I, the first and second information inputs n of the comparison circuit, respectively, with the output of the register of setting the cycle counter codes and the output of the cycle counter, the output of the fifth comparison circuit with the second input of the twenty-second element I, the outputs of the tenth one dinnadtsatogo and twelfth AND gates respectively with the first and third inputs .vtorym third OR gate, the output of the fifth AND gate - a clock input of the fourth comparing circuit. The drawing shows a block diagram of a device for debugging programs. The device contains the register 1 of the zone's initial address, the first 2 and the second 3 of the comparison circuit, the first element 4, the register 5 of the final zone address, the input 6 of the code of the device command address, the control register 7,. 8 register, third comparison circuit 9, third 10 and first 11 elements OR, second 12, third 13 and fourth 14 elements And, first 15, second 16 and third 17 groups of elements And, eighth 18, fifth 5, sixth 20 and the seventh 21 elements are AND, the first element is NOT 22, the first group is 23 elements OR, the ninth element is AND 24, the second element is OR 25, inputs 26-31 are signs of the address of a number, prize is the address of a command, signs of a team, the number of characters is , code of the device command, respectively, register 32 displays the fourth 33 fifth fifth 34 and sixth 35 groups: the elements AND, the register 36 is set and the codes of the number of the register of 37 assignment of the codes of the cycle counter, the register of the 38 unprogrammed instruction, the fourth 39 and fifth 40 comparisons, the counter of 41 cycles, the tenth 42J eleventh 43, twelve 1 44, thirteenth 45; 14th, 14th, 47th hexadecimals. 48 and seventeenth 49 elements AND, the fourth element of VDI 50, distributor 51 clock pulses;: ,, second 52 and third 53 elements NOT „twenty first 54, nineteen 555 twentieth 56 and twenty second 57 elements Kg fifth element OR 58, eighteenth element AND 59, col; howl shift register 60 ,, encoder 615 the second group of 62 elements of the SRI V5.od, s 63-67 start of the 1-kilo clock counter, number code ,, failure and control point of the device correspond - unprogrammed and randomly 68: device commands Registers start the zone 1 address is the final address of zone 5, control 7, the number 85 of setting the codes of the number 36 J for the counter-cycle codes,} for the 37 and iprogrammed comanier; -: .ip; saKjiroliiSTCK ::; next;

When the debugging feature has been created, by the operator on the toggle drive, with the current state of the computer with the state selected ;;: the system, in which the computer is running, at the output 68 of the unprogrammed command of the device, generated; y; .upg ; st unprogrammed commands to enter. E computer for the purpose of its cu. indication of the state of its register; .OE klk for cyclical plot

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The operation of the device begins with the uetanoBki on the registers of the beginning.

Zoo address and end address -: nh 5 of the beginning and end of the soi-ibi otpidkn (starting and ending addresses of viycrpaMiut or com.g.pekta programs. GGGdalzhny debugging)

When it is necessary to jam the area of the computer program during the debugging process, the operator sets the

To select the toggle register 7, the selected type of debug flag, and to which the io needs to organize the jamming of the program, and the Cycle mode. At the same time, at the output of the

The cycle of the tumbler control register 7 gives rise to a positive potential permitting the passage of the result of comparing the established debugging pattern with the current state. computer or with the state of the selected signals of the system in which the computer is embedded, from the code of the fifth element OR 58 5, which collects all possible options for comparison, etc. different

signs of debugging within the boundary conditions provided by the positive potential at the output of the first element I 4, through the eighth 18 and 048. During computer operation, the number of the command being executed through input 6 of the code of the address of the device command of the device is fed to the second inputs of the first and second circuits 2 and 3 of the comparison. At the output of the first comparison circuit 2, a full potential is present only if the command number is greater than the number dialed at register 1 of the start address of zone 15. At the output of the second comparison circuit 3, a positive polarity signal is present only if the command number is less than the number, dialed on the register 5 of the final address of the zone. Thus, the operation of the device in the zone of the programs to be debugged is ensured. Outside this zone, the operation of the device is blocked by zero potential from the output of the first element AND 4, which enters the input of the eighth element AND 18. The zero potential from the output of this element blocks the ninth 24 and eighteenth 59 elements AND, tacitly pulsed from the second output, distributes .. 51 clock pulses., determining the options for time. and the installation of computer response to information received from the output 68 of the unprogrammed device command. Thus, the presence of a null information given at the output 68 of the non-programmed device command does not affect the operation of a computer whose program

Eighteenth 59 elements And to the lane, left inputs of elements And the sixth group

35, the operation of the eighteenth element I 59 is clocked by signals from the second output of the clock distributor 51 connected via the clock input 64 of the device to the clock generator of the computer, which provides the necessary transmission timing diagram in the computer installed on the toggle register 38 of the unprogrammed junction command npo-frame given address through elements AND of the sixth group 35, elements OR of the second group 62 and output 68 of the unprogrammed device command.

By setting the Stop mode on the toggle control register 7, the operator provides a positive potential at the output of the stop mode of this register, permitting the result of comparing the set debugging symptom to flow with the computer or to the state of the selected signals of the state of the fifth element OR 58 through the eighth 18th and ninth 24 elements AND to the input of the ring register 60 shift and at the same time prohibiting through the third element NO 53 on the eighteenth element AND 58 passing this result ata comparing at pervt -Log elemntov and the sixth group 35 providing content delivery tumbler neprogrammirovannoy command register 38 through elements

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OR of the second group 62 to the output 68 of the unprogrammed device command i Nine element And 24 is clocked by signals from the second output of the clock distributor 51, which provides the necessary timing diagram of transmission to the computer of unprogrammed computer stop commands and indication of the contents of its registers formed on the encoder 6 in accordance with each state of the ring register 60 shift, through the elements OR of the second group 62 and. output 68 of the unprogrammed device command,

It is possible to operate the device with the following debugging signs set by the operator on the toggle control register 7 with the purpose of organizing the shutdown of a computer or cycling 880410. sections of its program: Address of a number (address of a command, address of a memory cell in which a read or write access occurs), Address of a command (number of the command being executed), Command (contents of the command being executed), Number ( the contents of the operand), the number-address of the number (the contents of Ada opera0 when referring to a certain

the memory location), the number-address of the command (the contents of the operand when executing a command with a certain number), the number-command (the contents

5 operands when executing a given command), Cycle counter (contents. Cycle counter), Failure (failure in the serviced system), Test point (any signal supplied

0 external jumper to the input of the control point of the device).

When setting the debug sign, the Address number at the output of the sign of the number of toggle control register 7 appears positive potential allowing the control signal to pass from the computer accompanying each access to the computer memory, through one 26 of the sign of the device number address, the second And 12 , the first element OR 11 on the clock input of the third circuit 9 comparison. At the same time, passing the contents of the address

5 part of the command executed in the computer through the input 30 of the code of the device number address, elements AND of the first group 15, elements OR of the first group 23 to the second information input, a third of the comparison circuit 9. This provides a comparison of the address part of each current command for accessing the computer memory with the contents of the toggle register of the 8th number in the third comparison circuit 9. In the case of a comparison, the positive potential from the output of the third comparison circuit 9 through the twenty-first element AND 54, the fifth element OR 58, the eighth element And 18,

and further, depending on the set Stop or Cycle mode, through the ninth 24th or eighteenth 59 elements I enter the generation of unprogrammed computer 5 stop commands and indication of the state of its registers with the help of ring shift register 60 and saffron 61 or unprogrammed commands 11

the course using the toggle register 38 unprogrammed commands and the elements of the sixth group 35 for issuing the generated information through the elements OR of the second group 62 and the output 68 of the unprogrammed device command to the computer.

When setting the debug flag, the command address is the positive potential arising from the output: the physical address of the command of the toggle control register 7 cuts off the passage of the control signal from the computer accompanying the activation of each command to the computer, through input 27 of the sign of the device command address, the third element And 13 , the first element OR 11 to the clock input of the third circuit 9 comparison and the passage of the contents of the address of the command executed in the computer through the input 6 of the code of the device command address, the elements of the second group 16, the elements OR of the first group ppy 23 to a second input of the third comparing circuit 9. This makes a comparison of the current address of the ZM command with the contents of the toggle register 8 numbers. The rest of the device operation is similar to the debug sign. The number address.

Setting the adjustment attribute The command on the toggle control register 7 causes a positive potential at the output of the command code of this register, allowing the control signal to pass from the computer that accompanies the execution of each command to the computer through the input 28 of the command signal; the device, the fourth element AND 14, the first element OR 11 at the clock input of the third comparison circuit 9 and passing the contents of the command executed in the computer through the input 31 of the command code of the device, the elements of the third group 17, the elements of the first group 23 to the second input of the third circuit 9 comparison, thereby making a comparison of the content; south of the current computer command with the contents of the toggle register In the number of Further operation of the device is similar to the work with the sign of debugging Address .number

By setting the debug flag, the operator causes a positive potential at the output of the toggle control register number code code 7, allowing the passage

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control, his signal from the computer, accompanying the junction of each operand in the computer, through the input 29 of the device number sign and the fifth element with AND 19 to the clock input of the fourth comparison circuit 39 and passing the contents of the operand from the computer through the input 65 of the device number code, elements and n of that group 34 to the second entrance

0 of the fourth comparison circuit 39. If the contents of the operand coincide with the contents of the toggle register 36, specify the number code positive potential from the EXIT of the fourth circuit

5 39 comparisons through the twentieth element AND 56 are fed to the input of the fifth element OR 58 and further causes the output of information from the output 68 of the unprogrammed device command in the same way as with the debug sign Address number „

When working with a debug flag, the number-address number of the positive potentials occur simultaneously

5 5. at the outputs of the address sign of the number and the sign of the number of the control toggle register 7. This causes the address part of the command and the contents of the operand to be compared with

Q contents of toggle registers 8 and 36 of the number and setting of the number code, and a positive potential at the output of the tenth element AND 42, which through the third element OR 10 allows the comparison results to pass from the outputs of the third 9 and fourth 39 comparison circuits; collected together on element N 55 and 55, to the input of the fifth element OR 58 simultaneously through the first element NOT 22, prohibits

Separate passage of the comparison results at the twenty-first 54 and twentieth 56 elements I. Further operation of the device is similar to the work with the sign of debugging. Address of the number.

The difference when working with debugging signs is the number-address of the command and the number-command that positive potentials arise

respectively on pairs of exits

the indication of the address of the command and the indication of the number or indication of the instruction and the indication of the number of the control tumbler register 7, in comparison with

the contents of the operand involve the address of the instruction being executed or, respectively, the contents of the instruction being executed, and for selecting the established debugging attribute when switching the outputs of the third 9 and fourth 39 comparison circuits, respectively, eleventh 43 or twelfth elements AND are used, the counter of 41 cycles is used to organize a computer stop or looping its program sections from one of three independent signal sources: the first output of the 51 clock pulse distributor, whose input is connected via clock input 6 4 devices to the clock pulse generator of the computer, signals Failure coming through the input 66 of the device failure, or any signal supplied by an external jumper to the input 67 of the control point of the device. The switching of the signal sources connected to the counting input of the loop counter 41 is carried out by the operator on the toggle control register 7e. When the dispenser 51 clock pulses are set as the source of the first output signals of the toggle control register 7 time count output, a positive potential arises, which allows clock pulses to pass when starting the cycle counter of the positive control signal device at the input 63. the first code of the distributor 51 clocks; pulses through the thirteen elements. AND 45 and the fourth element OR 50 to the counting input of the counter 41 cycles. Control signal The start at the input 63 of the start of the cycle counter of the device is necessary to prevent clock pulses from entering the counter for 41 cycles before the start of the computer to synchronize the initial time point on the counter of the computers with the start of operation of the computer on a given program area. To connect as the source of the counter signals 41 cycles, the Failure signal or the control point signals at the outputs of the reset account counting or the control settings of the control signal of the control tumbler register 7 are respectively set to a positive potential allowing the signals to pass. Failure of the fourteenth element OR 50, or, respectively, 4U signals from the inputs 67 of the control point of the device through the fifteenth element AND 47, the third element OR 50 to the counting input of the counter 41 cycles. When working with a debug sign, the Cycle Counter, the operator sets on the toggle control register 7 the necessary type of source of the loop counter 41 signals and the debug sign of the Cycle Counter, thereby connecting the required signal source to the counting input of the loop counter 41 and at the same time the positive potential is set to the output of the counter characteristic of the cycles of the toggle control register 7, allowing the passage of the comparison result from the output of the fifth comparison circuit 40 through the twenty-second element 57 to the input of the fifth element STI 58. Counting pulses from the selected source signals respectively received through one of elements of ex-tr I: thirteenth 45 chetfnadtsaty 46 or claim 47 fifteenth, fourth OR gate 50 to the input of the counter 41 cycles. Simultaneously from the output of the fourth element OR 0, the second element NOT 52 prohibits the operation of the fifth comparison circuit 49 at the transient time in the counter 41. Conversely, in the absence of counting pulses, the contents of the cycle counter 41 of the counter codes of the counter codes 37 are allowed to be compared in the same way. cycles in the fifth comparison circuit 40. Further operation of the device at the sign of debugging. The cycle counter is similar to the operation of the device with the sign of debugging. Address number. Io When working with debugging signs Failure or Checkpoint, a positive potential is set, respectively, at the outputs of the sign of failure and the sign of the control point of the toggle control register 7, allowing, respectively, the passage of signals Failure through the input 66 of the device and the sixteenth element 48 points of the device through the seventeenth element AND 49 into the fifth or sixth inputs of the fifth element OR 58. The further operation of the device is similar to the work with the sign of debugging Address numbers. Compatible from the point of view of simultaneous use are one of the group of mutually exclusive features: Address Number, Command Address, Command, Number Number Address Number, Number-Address Command Number-command with an arbitrary combination of independent acknowledgments: Loop counter, Fault, Checkpoint. To organize dynamic display of the operand contents when accessing computer memory by debugging signs, the Number Address or Command Address is used by the sixth 20 and seventh 21 AND elements, the second OR 25 element, And the fourth rpynnbi 33 elements and the display register 32. When dynamically indicating the contents of the operand, the address of the memory cell to which the computer is accessed (on the basis of debugging) Address numbers) the positive potential is set at the outputs of the number address attribute and the indication indicator of the number of toggle control register 7 code allowing the passage of the comparison of the cell address the memory, which is accessed in the computer, with the contents of the tumbler register of the 8th day (similar to working with the debug sign) Number address) from the output of the third comparison circuit 9 through the sixth ale the ent, the second element OR 25 to the first inputs of the elements AND of the fourth group 33, thereby ensuring the recording of the contents of the operand when accessing a given memory cell through the input 65 of the code of the device number, the elements of the fourth group 33 in the register 32 indi, cation. The difference in device operation when organizing dynamic indication of operand content by the command number (based on debugging indication) is the presence of a positive potential. The outputs of the command address and the indication of the toggle control register number code 7 permitting the comparison result to complete command with the contents of the toggle register of the 8th number (similar to working with the debug flag) Address of the command from the output of the third comparison circuit 9 through the seventh element And 21, in The second element is SH-25 at the first inputs of elements AND of the fourth group 33. The further operation of the device is similar to the method of organizing the dynamic display of the contents of the operand. Thus, the proposed device is an effective and operational means of debugging programs by providing a computer stop, indicating the state of its registers (on computer display means), looping sections of a program executed in a computer, and dynamically displaying the contents of the operand through a predetermined one or more compatible signs of debugging programs that take into account both the possible current states of the computer and the state of the system in which the computer is embedded that does not require the organization to zhnosti flow computer memory or disorder scale real-time its operation. Thus, the proposed device provides savings in the amount of computer memory and an increase in performance during debugging in comparison with the known device.

Claims (1)

DEVICE FOR DEBUGGING · PROGRAMS, containing the register of the starting address of the zone, the register of the ending address of the zone, the register of the number, the first, second and third comparison schemes, nine AND elements, three OR elements, the first NOT element, the control register, three groups of AND elements and the first group OR elements, and the information outputs of the register of the starting address of the zone and the register of the final address of the zone are connected respectively to the first inputs of the first and second comparison circuits, the outputs of which are connected respectively to the first and second outputs of the first ele ment And, the information output of the number register is connected to the first information input of the third comparison circuit, the output of the address sign of the number of the control register is connected to the first input of the second element And the first inputs of the elements And of the first group, the output of the address sign of the command of the control register is connected to the first input of the third element And and the first inputs of the AND elements of the second group, the input of the command code attribute of the control register command is connected to the first input of the fourth AND element and the first inputs of the AND elements of the third group, the output is recognized aka the code of the number of the control register is connected to the first input of the fifth element And, the output of the indication flag of the code of the number of the control register is connected to the first inputs of the sixth and seventh elements And, the outputs of the second, third and fourth elements And and the outputs of the elements And of the first, second and third groups are connected respectively with the first, second and third inputs of the first OR element and with the first, second and third 5 inputs of the OR elements of the first group, the output of the first OR element is connected to the clock input of the third circuit, comparison, the second information the input of which is connected to the outputs of the OR elements of the first group, the output of the first element AND is connected to the first input of the eighth element AND, the inputs of the sign of the address of the number, the sign of the command address, the sign of the command, the address code of the number, the address code of the command, the command code and the sign of the number of the device are connected with the second inputs of the second, third and fourth elements of And, respectively, with the second inputs of the elements of the first, second and third groups and the second input of the fifth element of And, the outputs of the sixth and seventh elements of And are connected respectively to th and the second inputs of the second OR gate, the input device instruction address code is coupled to the second data inputs of the first and second comparison circuits, characterized in that, with 1138804 .. in order to save memory and increase performance during debugging, the display register, the register for setting the number codes, the register for setting the codes of the cycle counter, the register of the unprogrammed commands, the fourth and fifth comparison circuits, the clock distributor, the cycle counter, the encoder, the ring shift register, the second and third elements are NOT, the fourth and fifth elements are OR, the fourth, fifth 1 and sixth groups of elements AND, the second group of elements OR and thirteen elements AND, and the output of the second OR element with it is single with the first inputs of the And fourth fourth element, the group of outputs of which is connected to the information input of the display register, the input of the device number code is connected to the second inputs of the And elements of the fourth group and with the first inputs of the And elements of the fifth group, the output group of which is connected to the first information input of the fourth comparison schemes, the information output of the register for setting the number codes is connected to the second information input of the fourth comparison scheme, the output of the code sign of the number of the control register is connected to the first inputs Dams of the tenth, eleventh and twelfth elements And and the second inputs of the elements And the fifth group, the output of the sign of the address of the number of the control register is connected to the second inputs of the sixth and tenth elements of And, the output of the sign of the address of the command of the control register is connected to the second inputs of the seventh and eleventh elements And, the output of the sign the control register command code is connected to the second input of the twelfth element AND, outputs of setting the time count, setting the count of failures, setting the count of signals of the control point, output of the sign of failure , the output of the sign of the control point, the stop mode and the cycle mode of the control register are connected to the first inputs of the thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, ninth and eighteenth elements AND, the output of the third OR element is connected to the first input of the nineteenth AND element and through the first element NOT with the first inputs of the twentieth and twenty-first elements AND, the output of the third comparison circuit is connected to the third inputs of the sixth and seventh elements AND, the second inputs of the nineteenth and twenty l of the first AND element, the outputs of the thirteenth, fourteenth and fifteenth AND elements are connected respectively to the first, second and third inputs of the fourth OR element, the output of which is connected to the counting input of the cycle counter and through the second element NOT to the clock input of the fifth comparison circuit, the output of the counter sign control register cycles connected to the first input of the twenty-second element And the outputs of the twenty-first, nineteenth, twentieth, twenty-second, sixteenth and seventeenth elements And are connected respectively the first, second, third, fourth, fifth and sixth inputs of the fifth OR element, the output of which is connected to the second input of the eighth element And, the output of the fourth comparison circuit is connected to the third input of the nineteenth element And and the second input of the twentieth element And, the output of the eighth element And is connected to the second inputs of the ninth and eighteenth elements AND, the outputs of which are connected respectively to the clock input of the annular shift register and the first inputs of the elements AND of the sixth group, the register output of the unprogrammed command is connected to the second inputs of the AND elements of the sixth group, the outputs of which are connected to the first inputs of the OR elements of the second group, the information output of the ring shift register is connected to the input of the encoder, the output of which is connected to the second inputs of the OR elements of the second group, the outputs of which are the outputs of the unprogrammed device command, counter start input cycles, the clock input, the input of the failure and the input of the control point of the device are connected respectively to the second input of the thirteenth element And, the clock input of the clock distributor impu sov, the second input of the fourteenth and sixteenth · u and the second inputs of the fifteenth and seventeenth element and first and second outputs of the clock pulse distributor are connected respectively to the third input them thirteenth AND gate and the third input of the ninth AND gate, 1 138804 the second output of the clock distributor is connected to the third input of the eighteenth AND element, the output of the stop mode of the control register through the third element is NOT connected to the fourth input of the eighteenth AND element, the first and second information inputs of the fifth comparison circuit are connected respectively to the output of the register register of the cycle counter codes and the output of the loop counter, the output of the fifth comparison circuit is connected to the second input of the twenty-second element And the outputs of the tenth, eleventh and twelfth elements And are connected to os / respectively with the first, second and third inputs of the third OR element, the output of the fifth AND element is connected to the clock input of the fourth comparison circuit.