SU1136170A1 - Device for registering trace of program execution - Google Patents

Abstract

A DEVICE FOR FIXING A PROGRAM EXECUTION ROUND, containing an address register, a previous address register, a first counter, a comparison unit, a memory unit, a firmware control unit, a switch and an OR element, the output of the address register is connected to the previous address register input and the first information input of the comparison unit , the output of the register of the previous address is connected to the second input of the comparison block, the outputs of equality and inequality of which are connected respectively to the counting input of the first counter and the address input b The first, second, third, fourth, and fifth outputs of the microprogram control unit are connected to the address register record input, the previous address register record input, the first counter initial setup input, the comparison unit resolution input, and the memory block record input, The information input of the switch is connected to the information input of the device, the information output of the first counter is connected to the first information input of the memory block, characterized in that in order to improve the speed when debugging programs, a number register, a row counter, a second counter, an associative memory block, and the sixth, seventh, eighth, ninth, tenth and eleventh outputs of the microprogrammed control block are connected to the counter input of the row counter , the control input of the switch, the input of the record of the number register, the input of the access to the associative memory block, the output of the stop by the device overflow, and the output of the stop by the fault of the device, the input of the mode the device is connected to the first input of the branch of the firmware control block, the switch output is connected to the information input of the number register, the output of the register of the number i is connected to the information input of the associative memory block and information (L output of the device, the output of row counters is connected to the input of the OR element and the older information the bits of the associative memory block, whose information output is connected to the address input of the rows of the memory block and to the first information input of the row counter, the output of the code to The numbers of the selected cells and the output of the zone address code oo are connected respectively to the second branch input of the firmware control unit and the first information input of the address register, the device address input is connected to the second information one. the input of the address register, the output of which is connected to the address of the zone address of the memory block and the address input of the associative memory block, the inequality output of the comparison block is connected to the counting input of the second counter, the output of which is connected to the second information input of the memory block, the information output of the memory block connected to the second information input of the row counter and the switch, the output of the OR element is connected to the input of the overflow sign of the firmware control unit.

Description

The invention relates to the field of computer technology, in particular, to the organization of monitoring and debugging programs.

A program control device is known that contains a command counter that counts sequentially executed commands, a register for storing the contents of the command counter in the case when a transition command is executed, and the register contents are output to the device in case of an error, AND, OR, block elements output 1.

A device is known for capturing the last addresses of implemented transition instructions, which contains a stack-type memory block with indication means, controlled by a counter of the number of transition commands, an instruction address register, an executive address register, a computer interrupt circuit, a main memory 2.

The drawback of the devices lies in their poor performance, which is a consequence of the formation of a sequence of program events with an indication of the number of cycles of their execution, i.e. the program execution trace after its running into the computer.

The closest in technical essence to the present invention is a device for monitoring program progress, comprising an address register, a previous address register, a cycle counter, a comparison unit, a memory block, a control unit, the output of the address register being connected to the information input of the previous address register and the first information the input of the comparison unit, the second information input of which is connected to the output of the register of the previous address, the first output to the counting input of the loop counter, and the second to the first input of the control unit, n The first, second, third, fourth, and fifth outputs of which are associated respectively with the control inputs of the address register, the previous address register, the cycle counter, the compare unit, and the memory block 3.

A disadvantage of the known device is also low productivity, which is a consequence of the formation of a program trace after its execution.

The purpose of the invention is to improve the performance of the device by automatically generating a program trace during its execution.

The goal is achieved in that a device for recording a program execution trace comprising an address register, a previous address register, a first counter, a comparison unit, a memory unit, a firmware control unit, a switch and an OR element, the output of the address register being connected to the previous register input. the address and the first information input of the comparison block, the output of the register of the previous address is connected to the second input of the block

comparison, the outputs of equality and inequality of which are connected respectively to the counting input of the first counter and the first address input of the microprogram control unit, the first, second, third, fourth and fifth outputs of the microprogram control block are connected respectively to the input of the address register entry, the input of the previous address register entry, the input of the initial installation of the first counter a, the resolution of the comparison unit comparison and the recording input of the memory unit, the information input of the switch is connected to the information m device input, information output of the first counter

5 is connected to the first information input of the memory block; a number register, a row counter, a second counter, an associative memory block, and the sixth, seventh, eighth, ninth, tenth and eleventh outputs of the microprogrammed control unit are entered.

0 are connected respectively to the counting input of the row counter, the control input of the switch, the input of the register of the number, the access address to the associative memory block, the output of the device overflow stop and the output of the device malfunction stop, the mode setting input of the device is connected to the first branch input microprocessor control unit, the switch output is connected to the information input of the number register,

The output of the register of numbers is connected to the information input of the associative memory block and the information output of the device, the output of row counters is connected to the input of the OR element and to the higher information bits of the associative memory block whose information output is connected to the address input of the rows of the memory block and the first information input of the row counter, the output of the cell number code and the output of the zone address code are connected

0, respectively, with the second branch input of the firmware control unit and with the first information input of the address register, the device address input connected to the second information address input input, the output of which is connected to the input

 the address of the memory block zone and the address input of the associative memory block, the output of the comparison block inequality is connected to the counting input of the second counter, the output of which is connected to the second information input of the memory block, the information output of the memory block is connected to the second information input of the row counter and the switch, the output of the element OR is connected to the input of the sign of overflow of the firmware control block.

FIG. 1 shows a functional diagram of a device for fixing a program execution trace; in fig. 2 - functional block firmware circuit

management; in fig. 3 is a functional block diagram of an associative memory; in fig. 4-8 is a block diagram of a device operation algorithm.

The device for fixing the program execution trace contains a register of 1 number, a register of 2 addresses, a register of 3 previous addresses, a 4.1 cycle counter, a sequence counter 4.2, a comparison block 5, an associative memory block 6, a memory block 7, a microprogram control block 8, group 9 control inputs, information input 10, address input 11, information output 12, fault stop 13.1, overflow stop 13.2, 14 lines counter, switch 15, OR element 16.

The first information input of the address 2 register is the device address input, the second information input is connected to the output address of the block 6 of the associative memory, the output is connected to the address input of the block 6 of the associative memory, to the address input of the zones of the memory block 7, with the first inputs of the register 3 the previous address, block 5 of the comparison, the second input of which is connected to the output of the register 3 of the previous address, the first output to the input of the counter 4.1 cycles, the second output to the input of the counter 4.2 sequential. the heat input and the first input of block 8, the outputs of counters 4.1 and 4.2 are connected to the group of information inputs of memory block 7, the output of which is connected to the second inputs of switch 15 and 14 rows, the outputs of 14 rows and 1 register are output of device information 12 and connected to the information input of the associative memory unit 6, the information output of which is connected to the input address of the row of the memory block and the first information input of the counter 14 lines, the output of the counter 14 lines connected to the input of the element OR 16, the output of which is connected to The first input of control unit 8, the third input of which is associated with the polling output of the associative memory block 6, the fourth input is a group of 9 control inputs, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth outputs connected respectively to the control inputs of the address register 2, the register 3 of the previous address, the 4.1 cycle counter, the comparison block 5, the 14-row counter, the switch 15, the number 1 register, the associative memory block 6, the tenth output is the fault stop output 13 devices, first inform insulating the switch input 15 is an input device 10, the information output of the switch 15 is connected to the data input of the register number 1.

The microprogram control unit 8 contains a fixed memory block 17, a micro-command address decimator 18, a micro-command address register 19, a micro-command modifier 20, an initial installation input 21.

the input of the permanent memory unit is connected to the output of the microinstructor address decoder, the input of which is connected to the output of the microinstruction address register; the input of the microinstruction address register 5 is connected to the output of the microinstruction address modifier, the first, second, third, fourth inputs of which are connected respectively to the first, second, the third, fourth inputs of the control unit, the fifth input is the initial input

 the unit is connected to the twelfth output of the permanent memory unit, the first to the eleventh outputs of which are connected respectively to the first to the eleventh outputs of the control unit.

5 The firmware control unit 8 operates in accordance with the firmware recorded in the fixed memory block 17 according to the clock signals of the pulse generator, the clock pulse input is included in group 9 of the control inputs. Signal processing

0 from device blocks is produced by modifier 20.

Block 6 of the associative memory consists of registers 22 polls, 23.1 masks for writing, 23.2 masks for reading, 24.2 ... 24.p memory,

5 blocks 25.1 ... 25.P of comparison, threshold block 26 of adder 27 modulo 2, decipher 28, switch 29, multiplexer 30, encoder 31, and the information input of the associative memory block 6 is connected to the information inputs of the write mask registers 23.1 and 23.2 of a mask for reading, n memory registers, the first group of information inputs and comparison units; the output of each of the memory registers is connected to the second group of information inputs of the corresponding

the comparison unit and with the corresponding information input of the multiplexer, the outputs of the register of masks are written to the inputs of the mask of each of the memory registers; the outputs of the register of the mask by reading

connected to the inputs of each of the comparison blocks, the output of each of which is connected to the corresponding information input of the poll register, the output of which is connected to the inputs of the threshold block, modulo 2 adder and decoder, output

5 which is the output of the address of block 6 of the associative memory and is connected to the first input of the switch, the second input of which is the input of the address of the block, and the output is connected to the address inputs of the multiplexer

Q and decoder, the first, second, pth output of the decoder is connected to the corresponding memory register, and the control input is connected to the control input of the associative memory block 6, which is also connected to the control inputs of the registers

5 polling, write masks, read masks, the switch, the outputs of the threshold unit and the modulo-2 adder are connected to the polling output of the associative memory block 6.

The block B of the associative memory stores the addresses of all commands of interest to the operator, each cell of block b corresponds to a memory zone of block 7 with a capacity of 2 cells. In block 7 of memory, a program execution trace is formed in the computer. The fact of the execution of any command specified by the operator is not only recorded, but the order of execution of each command in the computer (including repeated and so on) its use is indicated, with repeated execution of any command (execution of cyclic program sections) reflected by the number cycles written in one line with the order of the event. The order of numbering is end-to-end for all events of interest to the operator and does not depend on how many times (or not at all) one or another event from the set specified by the operator is executed.

Registers 2 and 3, comparison unit 5, cycle counter 4.1 are used for counting cycles, sequence counter 4.2 for numbering the order of events, number register 1 for inputting information, counter 14 for setting free line in memory block 7 .

The word length L of block 6 of the associative memory is 6 bits more than the size of the monitored information (the addresses of the commands executed in the computer).

When the counter overflows with 14 lines, its content takes the value 00 ... O, at the output of the OR 16 element, the logical “O. According to the output state of the element OR 16, the control unit 8 receives information about the overflow of the counter of 14 lines. The device can operate in three modes: input of information, control of the computational process with simultaneous formation of a trace and output of the resulting trace.

In the initial state (the setup circuits of the device blocks in the initial state are not shown as insignificant) all registers, cells of memory block 7, block 6 of associative memory contain code 00 ... O, and in counters 4.1 cycles and 4.2 sequences the code is set 0 ... 01. The device always starts its work in the information input mode, therefore the control unit 8 in its initial state waits for the "Write to device" signal, switch 15 connects information input 10 to the input of the 1st register (blocks 32-34 of the algorithm).

The information input mode is set by the potential signal “Write to the device from the input in group 9. From input 11, the cell address of the associative memory block 6 is written to the address register 2, and from input 10, the control information is written to the address register 1. Then the control information is entered into the block B of associative memory, respectively, the address stored in register 2. The control information is the addresses of computer commands, the execution of which interests the operator. Writing to register 1 and 2 and to block 6 of the associative memory is performed using the clock signals C1 and C2 from the control inputs of group 9 (blocks 35-40 of the algorithm).

The sequence of actions is repeated until the entire array of commands of interest to the operator is entered into block 6 of the associative memory. Then the "Write to device" signal is removed and it goes into the control mode of the computational process.

The internal computer signal "The end of the operation in the monitoring mode is sent to the control input of group 9. The same signal starts the operation cycle of block 8, which records from the input 10 in register 1 of the address number executed in the controlled computer command (blocks 41-43

algorithm), then a polling of block 6 of associative memory (blocks 44-47 of the algorithm).

If the contents of the register are 1, i.e. the address of the command executed in the computer does not coincide with the associative features of the cells of block 6, the device operation cycle ends, it goes into the waiting state of the address of the next command executed (blocks 48, 33, 34 and 41 of the algorithm).

If the contents of register 1 of a number coincide simultaneously with several association signs, then block 6 of associative memory generates a multiple match signal, which is perceived by control block 8 as a fault signal, block 8 generates a fault signal

on output 13 (blocks 50, 69 of the algorithm).

If the contents of register 1 of the number coincides with the associative feature of one of the cells of the block b of the associative memory, then the block b forms a single signal

the match that goes to control block 8, the processing cycle of the address of the executed command continues. By the signal of the control unit 8, the address of the block 6 of the associative memory is recorded in the address register 2, with the associative feature of which a match has occurred, then the comparison block 5 is polled.

If the contents of register 2 and the contents of register 3 (i.e., the addresses of the cells of block 6 of the associative memory that worked this and the previous time) are equal, the cyclic program section is executed, then one is added to the cycle counter 4.1. The device enters the waiting state of the address of the next command executed in the computer (blocks 52,49,33,34, 41 algorithms).

If the contents of register 2 and the contents of register 3 are not equal to each other (i.e., different cells of the associative memory block 6 are working in the present and the previous time), the linear portion of the program is executed, then one is added to the event sequence counter 4.2 and the block 8 control receives an inequality signal. After the arrival of this signal, control unit 8 organizes the recording of the contents of counters 4.1 and 4.2 in the cell of memory block 7, the high-order bits of whose addresses (zone address) are in address register 2, and the lower bits (row address) come from the selected block cell 6 associative memory (the address of this particular cell is recorded in register 2). At the same time, the signals of the control block 8 record the 14 lines of the lower bits of the word from the selected cell of the block 6, then add the unit to its contents and at the same time thicken the counter of 4.1 cycles, and then write the modified contents of the counter of 14 lines to the block b associative memory at the address of the cell stored in register 2 addresses, i.e. at the address of the cell from which the reading was made. Now the contents of these bits indicate a new free cell in its zone of memory block 7. The processing cycle of the address of the command executed in the computer is completed, the device enters a state of waiting for a new address (blocks 53-56, 33,34,41 of the algorithm). . End of operation of the device in the control mode may occur LIO0 when the signal appears "Read from device, either due to stopping by a fault or by filling one of the zones of memory block 7. In this case, when adding the unit in the lower bits of the selected word of the associative memory block 6, the code 00 ... 0 is set again, the logical element "O" is generated at the output of the OR 16 element, according to which the control unit 8 generates the signal "Device stop by filling 13.2 (blocks 56, 72 algorithms). The device is transferred to the read mode by the signal "Read from the device from the control input of group 9. In the read mode, the switch 15 switches and connects to the number 1 register the output of memory block 7. Because of the length of the word of the memory block 7, a part of it when read is placed in register 1 (the older L bits), the other part of it is in the counter 14 lines. Each read cycle is carried out as follows: the address register 2 from input 11 records the zone address of the memory block 7 by the clock signal from the control input of group 9. The signal from the control block 8 from memory block 7 writes the word in the 1st register 1 and the counter 14 lines, which from output 12 of information is output from the device. Then, the 14 line row counter is recorded from block 6 and the row address is added to it, the new row address is recorded in block 6. The zone is read until the 14 line counter overflows, after which the next zone is read, and so on. (blocks 33, 58-68 algorithm). The operation of block 6 of the associative memory occurs as follows: in the initial state, all the registers of the block are reset to zero, the switch 28 is set to such a position that it connects the address 2 to the address inputs of the decoder 28. Unit 6 operates in write, poll and read modes. In the recording mode, writing to the addressable cells of the associative memory unit 6 is first performed. The "Record of the control unit 8" excites the output of the decimator 28 corresponding to the contents of the register 2 numbers, and the information from the register 1 numbers is written in the indicated cell. After the recording of the array of information is completed, the cells of the associative memory unit 6 are written into the registers 23.1 and 23.2 of the masks, which is performed from the 1-st register of the numbers by signals of the microprogram control unit 8. The masks are set in such a way that the recording is carried out only in the lower E bits of the word. In the polling mode, block 6 of the associative memory works as follows. In the case of coincidence of the information in register 1 of the number and the counter of 14 lines with the contents of one of the registers 24 i at the output of the comparison blocks 25 i connected to it, a potential is generated corresponding to the logical level "1. The polling signal of the microprogram control block 8 records 1 in the register 22 of the poll corresponding to the cell, the contents of which coincides with the information on the input of block 6. Since several units can be simultaneously recorded in the poll register 22, the threshold block 26 analyzes multiple matches. Block 26 generates a multiple match signal if two or more units are recorded in the poll register 22 (then it is a set of standard logic elements). The code contained in the poll register 22 is also fed to the input of the adder 27 modulo 2, a logical < 1 > output would be if the number of ones in the register code 22 is odd. Thus, if one unit is contained in polling register 22, then the output of a multiple match will be a logical "O and at the output of a one-time match," 1. If the poll register 22 does not contain a single unit, on both outputs of block 6 of the associative memory there will be a logical “O. The contents of the poll register 22 is fed to the inputs of the encoder 31, the outputs of which form the address of the triggered cell. This address arrives at the output of the associative memory unit 6 and is written to the address register 2 in the event that a one-time match signal is received at the input of the block 8, while the output of the multiplexer 30 is set to a code equal to the content of the selected associative memory cell. During the read, 14 lines of 1 lower order word are written to the counter at the address stored in register 2 addresses, the contents of which are enlarged and then written back to their original place. Ш 13.2 3 10 Thus, the proposed device performs the functions of known devices, however, unlike them, it automatically forms a program execution trace with an indication of the sequence of events and the number of cycles. The formed trace has been prepared for display. If you link each control command with specific coordinates, the track can be directly displayed on the screen of the device for displaying the main image. The use of the proposed device will make it possible to drastically improve the efficiency and efficiency of monitoring the execution and debugging of programs in specialized computers contained in control systems operating in real time.

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Claims (1)

A DEVICE FOR FIXING A PROGRAM EXECUTION CIRCUIT, comprising an address register, a previous address register, a first counter, a comparison unit, a memory unit, a firmware control unit, a switch and an OR element, the output of the address register being connected to the register input of the previous address and the first information input of the comparison unit, the register output of the previous address is connected to the second input of the comparison unit, the equality and inequality outputs of which are connected respectively to the counting input of the first counter and the address input of the block m control software, the first, second, third, fourth and fifth outputs of the microprogram control unit are connected respectively to the input of the address register entry, the input of the previous address register entry, the initial setting of the first counter input, the comparison enable input of the comparison unit and the memory block write input, information switch input connected to the information input of the device, the information output of the first counter is connected to the first information input of the memory unit, characterized in that, in order to increase The performance of the program during debugging is entered into the number register, line counter, second counter, associative memory block, and the sixth, seventh, eighth, ninth, tenth and eleventh outputs of the microprogram control block are connected respectively to the counting input of the line counter that controls the input a switch, an input for registering a number register, an input for accessing an associative memory block, with a stop output for device overflow, and a stop output for device malfunction, an input for setting device connection modes n with the first branch input of the microprogram control unit, the output of the switch is connected to the information input of the number register, the output of the number register is connected to the information input of the § § associative memory and device information output, the output of line counters is connected to the input of the OR element and to the higher information bits of the associative memory block , the information output of which is connected to the address input of the lines of the memory block and the first information input of the line counter, the code output of the number of selected cells and the output of the zone address code is connected respectively to the second branch input of the microprogram control unit and to the first information input of the address register, the device address input is connected to the second information. the input of the address register, the output of which is connected to the address of the zone address of the memory block and the address input of the associative memory block, the output of the inequality of the comparison block is connected to the counting input of the second counter, the output of which is connected to the second information input of the memory block, the information output of the memory block is connected to the second information the input of the line counter and the switch, the output of the OR element is connected to the input of the overflow sign of the microprogram control unit. SU., .. 1136170